From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FA2BC77B75 for ; Wed, 17 May 2023 14:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232374AbjEQO7j (ORCPT ); Wed, 17 May 2023 10:59:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232303AbjEQO70 (ORCPT ); Wed, 17 May 2023 10:59:26 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A962393E1 for ; Wed, 17 May 2023 07:58:56 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-556011695d1so12557817b3.1 for ; Wed, 17 May 2023 07:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684335535; x=1686927535; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=8jJ35DtNbRKB+WNziMleSSiJd5T6wAbvpTtW48pRcrc=; b=lKBvUUw2Vn96syerPxcDZE8E2exBej8Qb7LquIlOdgJx3jGYp5ksAsA0QVnAo/nwpW 2Pqmmb3BEwD7aGpyrQ2kqWU+kVsplbxKLthqOOWc+PDoImmrOOLWr0aEVQSkUDf+LIIB 0Tj/fY/g1tY2dN65yYIdvO3G/NoOYSuEVrPxzNEE2oKevgNYYLi5EaoIDG+MKi3tpnHk wcdIQL06vTNGYlSDaIxlGNjwlh/Uu5EN3klZKgagv2rugGSEIUhfMmNqT0J3x7m2gx/n rZoeXumF8pm028Ian1W1kWDXFofi5SZUQjkypWkmYWOTHK6GxEllZzSLp+718xsnwNcv sFVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684335535; x=1686927535; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=8jJ35DtNbRKB+WNziMleSSiJd5T6wAbvpTtW48pRcrc=; b=fETMVH2cs/5VrD9V1HG5yvhpnCN1JSg4CcJod6Vv9ZNrj0eqNuyzIOQaKwqAjw21kC jJU5pydmvAm+YwxCdHX01K09vIzPEJZVy1Ip+b5Yih7UJjXMrk4FiAb0EFi8gML6i+es 3D9t9FEc7DbbtvKPuVnus4wXVg0tSXQ2N4cxm4YGAAnULYEvbiG0EBQDxBNjuc/R9ALw apqq7dx5Y2D5ssiw0zfL/1mlTJNRarwfw8d7E1aZ64Q99XAv+s6h/b35MtKUgAFcLAoB earY0zGLMhfaQgyrNKikw4s40frZ3tS1aEvf6Wr0vu7f4vLqI0D7DxZg+Wz4wNFXZJTo GJZw== X-Gm-Message-State: AC+VfDwKo0E5FVWSEChY6pI2oHSXc6XL79nG8AJGAJrL9ijjOxHUCr8Q 2nHfIxKyZogERUiSamhv3c79lVILbAZ8 X-Google-Smtp-Source: ACHHUZ6Xm7nhwlZ+D6gLz7kiTfpTYaq3ElipX/SETPRjeTCx8hdgsnGs+yw+2XZ4ky6eAZ+u2VoPTXVxGB45 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:628b:7e78:d09b:39b]) (user=irogers job=sendgmr) by 2002:a81:aa0a:0:b0:54c:2409:c306 with SMTP id i10-20020a81aa0a000000b0054c2409c306mr23372095ywh.6.1684335535732; Wed, 17 May 2023 07:58:55 -0700 (PDT) Date: Wed, 17 May 2023 07:57:49 -0700 In-Reply-To: <20230517145803.559429-1-irogers@google.com> Message-Id: <20230517145803.559429-10-irogers@google.com> Mime-Version: 1.0 References: <20230517145803.559429-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Subject: [PATCH v1 09/23] perf x86: Iterate hybrid PMUs as core PMUs From: Ian Rogers To: Suzuki K Poulose , Mike Leach , Leo Yan , John Garry , Will Deacon , James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Kajol Jain , Jing Zhang , Kan Liang , Zhengjun Xing , Ravi Bangoria , Madhavan Srinivasan , Athira Rajeev , Ming Wang , Huacai Chen , Sandipan Das , Dmitrii Dolgov <9erthalion6@gmail.com>, Sean Christopherson , Raul Silvera , Ali Saidi , Rob Herring , Thomas Richter , Kang Minchul , linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rather than iterating over a separate hybrid list, iterate all PMUs with the hybrid ones having is_core as true. Signed-off-by: Ian Rogers --- tools/perf/arch/x86/tests/hybrid.c | 2 +- tools/perf/arch/x86/util/evlist.c | 25 +++++++++++++++++-------- tools/perf/arch/x86/util/perf_regs.c | 14 ++++++++++---- 3 files changed, 28 insertions(+), 13 deletions(-) diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests/hybrid.c index 941a9edfed4e..944bd1b4bab6 100644 --- a/tools/perf/arch/x86/tests/hybrid.c +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -3,7 +3,7 @@ #include "debug.h" #include "evlist.h" #include "evsel.h" -#include "pmu-hybrid.h" +#include "pmu.h" #include "tests/tests.h" static bool test_config(const struct evsel *evsel, __u64 expected_config) diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/evlist.c index 1b6065841fb0..03f7eb4cf0a4 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -4,7 +4,6 @@ #include "util/evlist.h" #include "util/parse-events.h" #include "util/event.h" -#include "util/pmu-hybrid.h" #include "topdown.h" #include "evsel.h" @@ -12,9 +11,6 @@ static int ___evlist__add_default_attrs(struct evlist *evlist, struct perf_event_attr *attrs, size_t nr_attrs) { - struct perf_cpu_map *cpus; - struct evsel *evsel, *n; - struct perf_pmu *pmu; LIST_HEAD(head); size_t i = 0; @@ -25,15 +21,24 @@ static int ___evlist__add_default_attrs(struct evlist *evlist, return evlist__add_attrs(evlist, attrs, nr_attrs); for (i = 0; i < nr_attrs; i++) { + struct perf_pmu *pmu = NULL; + if (attrs[i].type == PERF_TYPE_SOFTWARE) { - evsel = evsel__new(attrs + i); + struct evsel *evsel = evsel__new(attrs + i); + if (evsel == NULL) goto out_delete_partial_list; list_add_tail(&evsel->core.node, &head); continue; } - perf_pmu__for_each_hybrid_pmu(pmu) { + while ((pmu = perf_pmu__scan(pmu)) != NULL) { + struct perf_cpu_map *cpus; + struct evsel *evsel; + + if (!pmu->is_core) + continue; + evsel = evsel__new(attrs + i); if (evsel == NULL) goto out_delete_partial_list; @@ -51,8 +56,12 @@ static int ___evlist__add_default_attrs(struct evlist *evlist, return 0; out_delete_partial_list: - __evlist__for_each_entry_safe(&head, n, evsel) - evsel__delete(evsel); + { + struct evsel *evsel, *n; + + __evlist__for_each_entry_safe(&head, n, evsel) + evsel__delete(evsel); + } return -1; } diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c index 0ed177991ad0..26abc159fc0e 100644 --- a/tools/perf/arch/x86/util/perf_regs.c +++ b/tools/perf/arch/x86/util/perf_regs.c @@ -10,7 +10,6 @@ #include "../../../util/debug.h" #include "../../../util/event.h" #include "../../../util/pmu.h" -#include "../../../util/pmu-hybrid.h" const struct sample_reg sample_reg_masks[] = { SMPL_REG(AX, PERF_REG_X86_AX), @@ -286,7 +285,6 @@ uint64_t arch__intr_reg_mask(void) .disabled = 1, .exclude_kernel = 1, }; - struct perf_pmu *pmu; int fd; /* * In an unnamed union, init it here to build on older gcc versions @@ -294,12 +292,20 @@ uint64_t arch__intr_reg_mask(void) attr.sample_period = 1; if (perf_pmu__has_hybrid()) { + struct perf_pmu *pmu = NULL; + __u64 type = PERF_TYPE_RAW; + /* * The same register set is supported among different hybrid PMUs. * Only check the first available one. */ - pmu = list_first_entry(&perf_pmu__hybrid_pmus, typeof(*pmu), hybrid_list); - attr.config |= (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; + while ((pmu = perf_pmu__scan(pmu)) != NULL) { + if (pmu->is_core) { + type = pmu->type; + break; + } + } + attr.config |= type << PERF_PMU_TYPE_SHIFT; } event_attr_init(&attr); -- 2.40.1.606.ga4b1b128d6-goog