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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id t14-20020a17090b018e00b002532eef4fc5sm925013pjs.34.2023.05.24.02.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 02:25:50 -0700 (PDT) From: Andy Chiu To: palmer@dabbelt.com Cc: andy.chiu@sifive.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, remi@remlab.net Subject: Re: [PATCH -next v20 20/26] riscv: Add prctl controls for userspace vector management Date: Wed, 24 May 2023 09:25:30 +0000 Message-Id: <20230524092530.7773-1-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org How about adding the following 2 patches to deal with the problem. However, I am concerned if this makes ELF_HWCAP too complicated. e.g. Future extensions may as well want to do something here after we create an entry here. Thanks, Andy [-- Attachment #1: patch.diff --] From: Andy Chiu Date: Wed, 24 May 2023 08:00:11 +0000 Subject: [PATCH 1/2] riscv: hwcap: change ELF_HWCAP to a function Signed-off-by: Andy Chiu --- arch/riscv/include/asm/elf.h | 2 +- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index ca23c4f6c440..c24280774caf 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -66,7 +66,7 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr); * via a bitmap that coorespends to each single-letter ISA extension. This is * essentially defunct, but will remain for compatibility with userspace. */ -#define ELF_HWCAP (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)) +#define ELF_HWCAP riscv_get_elf_hwcap() extern unsigned long elf_hwcap; /* diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 574385930ba7..e6c288ac4581 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -61,6 +61,8 @@ #include +unsigned long riscv_get_elf_hwcap(void); + struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 28032b083463..29c0680652a0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -293,6 +293,11 @@ void __init riscv_fill_hwcap(void) pr_info("riscv: ELF capabilities %s\n", print_str); } +unsigned long riscv_get_elf_hwcap(void) +{ + return (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); +} + #ifdef CONFIG_RISCV_ALTERNATIVE /* * Alternative patch sites consider 48 bits when determining when to patch -- 2.17.1 [-- Attachment #2: patch2.diff --] From: Andy Chiu Date: Wed, 24 May 2023 08:00:11 +0000 Subject: [PATCH 1/2] riscv: hwcap: change ELF_HWCAP to a function Signed-off-by: Andy Chiu --- arch/riscv/include/asm/elf.h | 2 +- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index ca23c4f6c440..c24280774caf 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -66,7 +66,7 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr); * via a bitmap that coorespends to each single-letter ISA extension. This is * essentially defunct, but will remain for compatibility with userspace. */ -#define ELF_HWCAP (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)) +#define ELF_HWCAP riscv_get_elf_hwcap() extern unsigned long elf_hwcap; /* diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 574385930ba7..e6c288ac4581 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -61,6 +61,8 @@ #include +unsigned long riscv_get_elf_hwcap(void); + struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 28032b083463..29c0680652a0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -293,6 +293,11 @@ void __init riscv_fill_hwcap(void) pr_info("riscv: ELF capabilities %s\n", print_str); } +unsigned long riscv_get_elf_hwcap(void) +{ + return (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); +} + #ifdef CONFIG_RISCV_ALTERNATIVE /* * Alternative patch sites consider 48 bits when determining when to patch -- 2.17.1