From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
<stefank@nvidia.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
"Joe Perches" <joe@perches.com>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
Thierry Reding <treding@nvidia.com>
Subject: [PATCH v5 2/5] mailbox: tegra: add support for Tegra264
Date: Mon, 29 May 2023 16:50:45 +0300 [thread overview]
Message-ID: <20230529135044.2746339-3-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <20230529135044.2746339-1-pdeschrijver@nvidia.com>
From: Stefan Kristiansson <stefank@nvidia.com>
Tegra264 has a slightly different doorbell register layout than
previous chips.
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/mailbox/tegra-hsp.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 573481e436f5..7f98e7436d94 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/delay.h>
@@ -97,6 +97,7 @@ struct tegra_hsp_soc {
const struct tegra_hsp_db_map *map;
bool has_per_mb_ie;
bool has_128_bit_mb;
+ unsigned int reg_stride;
};
struct tegra_hsp {
@@ -279,7 +280,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
return ERR_PTR(-ENOMEM);
offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
- offset += index * 0x100;
+ offset += index * hsp->soc->reg_stride;
db->channel.regs = hsp->regs + offset;
db->channel.hsp = hsp;
@@ -916,24 +917,35 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = {
.map = tegra186_hsp_db_map,
.has_per_mb_ie = false,
.has_128_bit_mb = false,
+ .reg_stride = 0x100,
};
static const struct tegra_hsp_soc tegra194_hsp_soc = {
.map = tegra186_hsp_db_map,
.has_per_mb_ie = true,
.has_128_bit_mb = false,
+ .reg_stride = 0x100,
};
static const struct tegra_hsp_soc tegra234_hsp_soc = {
.map = tegra186_hsp_db_map,
.has_per_mb_ie = false,
.has_128_bit_mb = true,
+ .reg_stride = 0x100,
+};
+
+static const struct tegra_hsp_soc tegra264_hsp_soc = {
+ .map = tegra186_hsp_db_map,
+ .has_per_mb_ie = false,
+ .has_128_bit_mb = true,
+ .reg_stride = 0x1000,
};
static const struct of_device_id tegra_hsp_match[] = {
{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
{ .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
{ .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
+ { .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc },
{ }
};
--
2.34.1
next prev parent reply other threads:[~2023-05-29 13:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-29 13:50 [PATCH v5 0/5] firmware: tegra: Add MRQ " Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 1/5] dt-bindings: mailbox: tegra: Document Tegra264 HSP Peter De Schrijver
2023-05-29 13:50 ` Peter De Schrijver [this message]
2023-06-20 13:12 ` [PATCH v5 2/5] mailbox: tegra: add support for Tegra264 Peter De Schrijver
2023-06-20 15:08 ` Jassi Brar
2023-06-21 12:06 ` Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 3/5] dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 4/5] dt-bindings: firmware: Add support for tegra186-bpmp " Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 5/5] firmware: tegra: bpmp: Add support for " Peter De Schrijver
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