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Fri, 9 Jun 2023 09:29:19 GMT Received: from hu-pkondeti-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 9 Jun 2023 02:29:14 -0700 Date: Fri, 9 Jun 2023 14:59:10 +0530 From: Pavan Kondeti To: Konrad Dybcio CC: Pavan Kondeti , Rohit Agarwal , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 4/5] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible Message-ID: <20230609092910.GA558673@hu-pkondeti-hyd.qualcomm.com> References: <1686138469-1464-1-git-send-email-quic_rohiagar@quicinc.com> <1686138469-1464-5-git-send-email-quic_rohiagar@quicinc.com> <20230609050052.GA472607@hu-pkondeti-hyd.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: k6WSzfNCW1BVZXXpYe3YFe1eXrxFhw3M X-Proofpoint-GUID: k6WSzfNCW1BVZXXpYe3YFe1eXrxFhw3M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_06,2023-06-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090081 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 09, 2023 at 11:17:08AM +0200, Konrad Dybcio wrote: > > > On 9.06.2023 07:00, Pavan Kondeti wrote: > > On Wed, Jun 07, 2023 at 05:17:48PM +0530, Rohit Agarwal wrote: > >> Add compatible for EPSS CPUFREQ-HW on SDX75. > >> > >> Signed-off-by: Rohit Agarwal > >> Acked-by: Viresh Kumar > >> --- > >> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + > >> 1 file changed, 1 insertion(+) > >> > >> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > >> index a6b3bb8..866ed2d 100644 > >> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > >> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > >> @@ -36,6 +36,7 @@ properties: > >> - qcom,sa8775p-cpufreq-epss > >> - qcom,sc7280-cpufreq-epss > >> - qcom,sc8280xp-cpufreq-epss > >> + - qcom,sdx75-cpufreq-epss > >> - qcom,sm6375-cpufreq-epss > >> - qcom,sm8250-cpufreq-epss > >> - qcom,sm8350-cpufreq-epss > > > > This is a very basic question, not completely related to this patch. > > Apologies in advance. > > > > What is the rationale for adding a new soc string under compatible and > > using it in the new soc device tree? Is it meant for documentation purpose? > > i.e one know what all SoCs / boards supported by this device node. > It's two-fold: > > 1. The device tree describes the hardware, and for lack of better terms (e.g. > an SoC-specific version number of the block that is identical to all other > implementations of that revision on all SoCs that use it), we tend to > associate it with the SoC it's been (first) found on. > > 2. In case we ever needed to introduce a SoC-specific quirk, we can just add > an of_is_compatible-sorta check to the driver and not have to update the > device trees. This is very important for keeping backwards compatibility, > as it's assumed that not everybody may be running the latest one. This > means we have to avoid ABI breaks (unless we have *very* good reasons, like > "this would have never worked anyway" or "it was not described properly > and worked on this occasion by pure luck") > Thanks Konrad for the explanation. The #2 is a clear winner here. It makes complete sense. In devices like USB, we have PID/VID through which quirks can be implemented later. So I guess the same analogy applies here. Like you said in (1), the devices are identified with SoC compatible string. Thanks, Pavan