[PATCH 1/4] perf pmus: Describe semantics of 'core_pmus' and 'other_pmus'

[Ravi Bangoria <ravi.bangoria@amd.com>]

'core_pmus' and 'other_pmus' are independent of hw core pmu and uncore
pmus. For example, AMD IBS PMUs are present in each SMT-thread but they
belongs to 'other_pmus'. Add a comment describing what these list
contains and how they are treated.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
---
 tools/perf/util/pmus.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c
index e1d0a93147e5..e505d2fef828 100644
--- a/tools/perf/util/pmus.c
+++ b/tools/perf/util/pmus.c
@@ -12,6 +12,19 @@
 #include "pmu.h"
 #include "print-events.h"
 
+/*
+ * core_pmus:  A PMU belongs to core_pmus if it's name is "cpu" or it's sysfs
+ *             directory contains "cpus" file. All PMUs belonging to core_pmus
+ *             must have pmu->is_core=1. If there are more than one PMUs in
+ *             this list, perf interprets it as a heterogeneous platform.
+ *             (FWIW, certain ARM platforms having heterogeneous cores uses
+ *             homogeneous PMU in which case it will be treated as homogeneous
+ *             platform by perf because core_pmus will have only one entry.)
+ * other_pmus: All other PMUs which are not part of core_pmus list. Does not
+ *             matter whether it is a per SMT-thread or outside of the core in
+ *             hw. i.e. PMUs belonging to other_pmus must have pmu->is_core=0
+ *             but pmu->is_uncore could be 0 or 1.
+ */
 static LIST_HEAD(core_pmus);
 static LIST_HEAD(other_pmus);
 static bool read_sysfs_core_pmus;
-- 
2.40.1