[PATCH] x86/msr-index: Fix MSR_IA32_ARCH_CAPABILITIES bit ordering

[Daniel Sneddon <daniel.sneddon@linux.intel.com>]

When the definition of ARCH_CAP_XAPIC_DISABLE was added to
MSR_IA32_ARCH_CAPABILITIES it was incorrectly placed at the bottom of
the list instead of being inserted by bit order. This means
ARCH_CAP_XAPIC_DISABLE and ARCH_CAP_PBRSB_NO are now swapped and any
future additions may look out of place. Move ARCH_CAP_XAPIC_DISABLE to
its correct position.

No functional change.

Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
---
 arch/x86/include/asm/msr-index.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3aedae61af4fc..76b154e9aebaa 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -151,15 +151,14 @@
 						 * are restricted to targets in
 						 * kernel.
 						 */
-#define ARCH_CAP_PBRSB_NO		BIT(24)	/*
-						 * Not susceptible to Post-Barrier
-						 * Return Stack Buffer Predictions.
-						 */
-
 #define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
 						 * IA32_XAPIC_DISABLE_STATUS MSR
 						 * supported
 						 */
+#define ARCH_CAP_PBRSB_NO		BIT(24)	/*
+						 * Not susceptible to Post-Barrier
+						 * Return Stack Buffer Predictions.
+						 */
 
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
-- 
2.25.1