[RFC PATCH 5/6] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN

["Clément Léger" <cleger@rivosinc.com>]

Now that trap support is ready to handle misalignment errors in S-mode,
allow the user to control the behavior of misalignment accesses using
prctl(). Add an align_ctl flag in thread_struct which will be used to
determine if we should SIGBUS the process or not on such fault.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/processor.h   |  9 +++++++++
 arch/riscv/kernel/process.c          | 20 ++++++++++++++++++++
 arch/riscv/kernel/traps_misaligned.c |  7 +++++++
 3 files changed, 36 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 94a0590c6971..4e6667d5ca68 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -7,6 +7,7 @@
 #define _ASM_RISCV_PROCESSOR_H
 
 #include <linux/const.h>
+#include <linux/prctl.h>
 
 #include <vdso/processor.h>
 
@@ -39,6 +40,7 @@ struct thread_struct {
 	unsigned long s[12];	/* s[0]: frame pointer */
 	struct __riscv_d_ext_state fstate;
 	unsigned long bad_cause;
+	unsigned long align_ctl;
 };
 
 /* Whitelist the fstate from the task_struct for hardened usercopy */
@@ -51,6 +53,7 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
 
 #define INIT_THREAD {					\
 	.sp = sizeof(init_stack) + (long)&init_stack,	\
+	.align_ctl = PR_UNALIGN_NOPRINT,		\
 }
 
 #define task_pt_regs(tsk)						\
@@ -80,6 +83,12 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
+extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
+extern int set_unalign_ctl(struct task_struct *, unsigned int val);
+
+#define GET_UNALIGN_CTL(tsk, addr)	get_unalign_ctl((tsk), (addr))
+#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index e2a060066730..b8a41e3c1333 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -19,6 +19,7 @@
 #include <asm/unistd.h>
 #include <asm/processor.h>
 #include <asm/csr.h>
+#include <asm/sbi.h>
 #include <asm/stacktrace.h>
 #include <asm/string.h>
 #include <asm/switch_to.h>
@@ -40,6 +41,25 @@ void arch_cpu_idle(void)
 	cpu_do_idle();
 }
 
+int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
+{
+#if IS_ENABLED(CONFIG_RISCV_SBI)
+	if (!sbi_delegate_misaligned())
+		return -EINVAL;
+#endif
+	tsk->thread.align_ctl = val;
+	return 0;
+}
+
+int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
+{
+#if IS_ENABLED(CONFIG_RISCV_SBI)
+	if (!sbi_delegate_misaligned())
+		return -EINVAL;
+#endif
+	return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr);
+}
+
 void __show_regs(struct pt_regs *regs)
 {
 	show_regs_print_info(KERN_DEFAULT);
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index e4a273ab77c9..b828a0f3d4f7 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/stringify.h>
+#include <linux/prctl.h>
 
 #include <asm/processor.h>
 #include <asm/ptrace.h>
@@ -277,6 +278,9 @@ int handle_misaligned_load(struct pt_regs *regs)
 	if (!IS_ENABLED(CONFIG_RISCV_M_MODE) && !user_mode(regs))
 		return -1;
 
+	if ((current->thread.align_ctl & PR_UNALIGN_SIGBUS))
+		return -1;
+
 	if (get_insn(epc, &insn))
 		return -1;
 
@@ -373,6 +377,9 @@ int handle_misaligned_store(struct pt_regs *regs)
 	if (!IS_ENABLED(CONFIG_RISCV_M_MODE) && !user_mode(regs))
 		return -1;
 
+	if ((current->thread.align_ctl & PR_UNALIGN_SIGBUS))
+		return -1;
+
 	if (get_insn(epc, &insn))
 		return -1;
 
-- 
2.40.1