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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 0/9] Add support to handle misaligned accesses in S-mode Date: Tue, 4 Jul 2023 16:09:15 +0200 Message-Id: <20230704140924.315594-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture.") in the RISC-V ISA manual, it is stated that misaligned load/store might not be supported. However, the RISC-V kernel uABI describes that misaligned accesses are supported. In order to support that, this series adds support for S-mode handling of misaligned accesses, SBI call for misaligned trap delegation as well prctl support for PR_SET_UNALIGN. Handling misaligned access in kernel allows for a finer grain control of the misaligned accesses behavior, and thanks to the prctl call, can allow disabling misaligned access emulation to generate SIGBUS. User space can then optimize its software by removing such access based on SIGBUS generation. This series relies on a SBI extension [1] allowing to request delegation of the misaligned load/store traps to the S-mode software. This extension has been submitted for review to the riscv tech-prs group. An OpenSBI implementation for this spec is available at [2]. This series can be tested using the spike simulator [3] which allows to either handles misaligned access in hardware or let the software do it. With hardware misaligned access support: $ ./spike --misaligned --initrd=rootfs.cpio \ --kernel=arch/riscv/boot/Image opensbi_fw_jump.elf Without hardware misaligned access support: $ ./spike --initrd=rootfs.cpio --kernel=arch/riscv/boot/Image \ opensbi_fw_jump.elf [1] https://lists.riscv.org/g/tech-prs/message/540 [2] https://github.com/rivosinc/opensbi/tree/dev/cleger/fw_feature_upstream [3] https://github.com/riscv-software-src/riscv-isa-sim Changes in V2: - Fix prototypes declaration for handle_misaligned_load/store() - Fix build for !CONFIG_FPU - Added conditional build for various part of misaligned code handling - Added in-kernel misalignement fault support to be equivalent to existing SBI support - Added support for misalignment emulation detection for hwprobe reporting - Modified set/get_unaligned_ctl to use this detection of emulation - Added support for sysctl "unaligned_enabled" Clément Léger (9): riscv: remove unused functions in traps_misaligned.c riscv: avoid missing prototypes warning riscv: add support for misaligned handling in S-mode riscv: report perf event for misaligned fault riscv: add support for sysctl unaligned_enabled control riscv: add support for SBI misalignment trap delegation riscv: report misaligned accesses emulation to hwprobe riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN riscv: add floating point insn support to misaligned access emulation arch/riscv/Kconfig | 1 + arch/riscv/include/asm/cpufeature.h | 10 + arch/riscv/include/asm/entry-common.h | 3 + arch/riscv/include/asm/processor.h | 9 + arch/riscv/include/asm/sbi.h | 11 + arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/fpu.S | 117 +++++++++ arch/riscv/kernel/process.c | 18 ++ arch/riscv/kernel/sbi.c | 21 ++ arch/riscv/kernel/setup.c | 2 + arch/riscv/kernel/traps.c | 9 - arch/riscv/kernel/traps_misaligned.c | 352 ++++++++++++++++++++++---- 12 files changed, 498 insertions(+), 57 deletions(-) -- 2.40.1