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From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: aou@eecs.berkeley.edu, heiko@sntech.de,
	herbert@gondor.apana.org.au, davem@davemloft.net,
	conor.dooley@microchip.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
	christoph.muellner@vrull.eu, ebiggers@kernel.org,
	Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: [PATCH v4 03/12] RISC-V: add helper function to read the vector VLEN
Date: Tue, 11 Jul 2023 17:37:34 +0200	[thread overview]
Message-ID: <20230711153743.1970625-4-heiko@sntech.de> (raw)
In-Reply-To: <20230711153743.1970625-1-heiko@sntech.de>

From: Heiko Stuebner <heiko.stuebner@vrull.eu>

VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.

The vector code already includes a variable riscv_vsize that contains the
value of "32 vector registers with vlenb length" that gets filled during
boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".

So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.

Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
 arch/riscv/include/asm/vector.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index ac2c23045eec..88cf76a2316d 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -232,4 +232,15 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
 
 #endif /* CONFIG_RISCV_ISA_V */
 
+/*
+ * Return the implementation's vlen value.
+ *
+ * riscv_vsize contains the value of "32 vector registers with vlenb length"
+ * so rebuild the vlen value in bits from it.
+ */
+static inline int riscv_vector_vlen(void)
+{
+	return riscv_v_vsize / 32 * 8;
+}
+
 #endif /* ! __ASM_RISCV_VECTOR_H */
-- 
2.39.2


  parent reply	other threads:[~2023-07-11 15:39 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-11 15:37 [PATCH v4 00/12] RISC-V: support some cryptography accelerations Heiko Stuebner
2023-07-11 15:37 ` [PATCH v4 01/12] riscv: Add support for kernel mode vector Heiko Stuebner
2023-07-11 17:11   ` Rémi Denis-Courmont
2023-07-13 17:19     ` Andy Chiu
2023-07-11 15:37 ` [PATCH v4 02/12] riscv: Add vector extension XOR implementation Heiko Stuebner
2023-07-11 17:33   ` Rémi Denis-Courmont
2023-07-11 15:37 ` Heiko Stuebner [this message]
2023-07-11 18:06   ` [PATCH v4 03/12] RISC-V: add helper function to read the vector VLEN Rémi Denis-Courmont
2023-07-11 15:37 ` [PATCH v4 04/12] RISC-V: add vector crypto extension detection Heiko Stuebner
2023-07-12 10:40   ` Anup Patel
2023-07-18 14:55   ` Conor Dooley
2023-07-21  5:48   ` Eric Biggers
2023-07-11 15:37 ` [PATCH v4 05/12] RISC-V: crypto: update perl include with helpers for vector (crypto) instructions Heiko Stuebner
2023-07-11 18:04   ` Rémi Denis-Courmont
2023-07-11 15:37 ` [PATCH v4 06/12] RISC-V: crypto: add Zvbb+Zvbc accelerated GCM GHASH implementation Heiko Stuebner
2023-08-10  9:57   ` Andy Chiu
2023-07-11 15:37 ` [PATCH v4 07/12] RISC-V: crypto: add Zvkg " Heiko Stuebner
2023-07-11 15:37 ` [PATCH v4 08/12] RISC-V: crypto: add a vector-crypto-accelerated SHA256 implementation Heiko Stuebner
2023-07-21  4:42   ` Eric Biggers
2023-07-11 15:37 ` [PATCH v4 09/12] RISC-V: crypto: add a vector-crypto-accelerated SHA512 implementation Heiko Stuebner
2023-07-11 15:37 ` [PATCH v4 10/12] RISC-V: crypto: add Zvkned accelerated AES encryption implementation Heiko Stuebner
2023-07-21  5:40   ` Eric Biggers
2023-07-21 11:39     ` Ard Biesheuvel
2023-07-21 14:23       ` Ard Biesheuvel
2023-09-11 13:06     ` Jerry Shih
2023-09-12  7:04       ` Ard Biesheuvel
2023-09-12  7:15         ` Jerry Shih
2023-09-15  1:28           ` He-Jie Shih
2023-07-11 15:37 ` [PATCH v4 11/12] RISC-V: crypto: add Zvksed accelerated SM4 " Heiko Stuebner
2023-07-11 15:37 ` [PATCH v4 12/12] RISC-V: crypto: add Zvksh accelerated SM3 hash implementation Heiko Stuebner
2023-07-13  7:40 ` [PATCH v4 00/12] RISC-V: support some cryptography accelerations Eric Biggers
2023-07-14  6:27   ` Eric Biggers
2023-07-14  7:02     ` Heiko Stuebner
2023-07-21  5:12 ` Eric Biggers
2023-09-14  0:11 ` Eric Biggers
2023-09-14  1:10   ` Charlie Jenkins
2023-09-15  1:48     ` He-Jie Shih
2023-09-15  3:21       ` Jerry Shih
2023-10-06 19:47         ` Eric Biggers
2023-10-06 21:01           ` He-Jie Shih
2023-10-06 23:33             ` Ard Biesheuvel
2023-10-07 22:16               ` Eric Biggers
2023-10-07 21:30             ` Eric Biggers
2023-10-31  2:17           ` Jerry Shih
2023-11-02  4:03             ` Eric Biggers
2023-11-21 23:51               ` Eric Biggers
2023-11-22  7:58                 ` Jerry Shih
2023-11-22 23:42                   ` Eric Biggers
2023-11-23  0:36                     ` Christoph Müllner
2023-11-28 20:19                       ` Eric Biggers

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