From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92423C001DE for ; Fri, 14 Jul 2023 20:38:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236499AbjGNUiZ (ORCPT ); Fri, 14 Jul 2023 16:38:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236252AbjGNUiS (ORCPT ); Fri, 14 Jul 2023 16:38:18 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFBB235B0; Fri, 14 Jul 2023 13:38:09 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36EJiAlY011075; Fri, 14 Jul 2023 20:38:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=1rET9sqygklM/Vubbk6Gg7UOv/fTy97G2Ja8MS45kQQ=; b=B2Ie7kmF/aFMkWidx3nfiI0g6/5fkl0pxZ+jiBc/tTY+A7ai8zExOHRHRD52KFl3OMj0 gFjvZFxF2/dqWSdbx2b396d1GvpgMuatlRlEkjbofVhMiF7Dc1JJxYTe0TIapbBe08m3 mQVJCMka66Un2K7+ttcuh02axIJsjonVkw82KbKKAYn8mpp8jX3PRJ+nCpFZER3vr1mJ NnGOAO7EQ4TxdbLxU3NyWVI9wcUYFVrJV9GCgXgFBHeNk1+u7vtOvvwU7b/6/7VFFd+B 5N/8cFwZMIjfGrsL4njjISrk69mZw5oZhvaLkrdF+RKLsvdFyOD5y+B0oszdsV8MYuRb Sg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rtpubasp4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Jul 2023 20:38:06 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36EKc4gc019583 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Jul 2023 20:38:04 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Fri, 14 Jul 2023 13:38:03 -0700 Date: Fri, 14 Jul 2023 13:38:02 -0700 From: Bjorn Andersson To: Ninad Naik CC: , , , , , , , , Subject: Re: [PATCH] pinctrl: qcom: Add intr_target_width to define intr_target_bit field width Message-ID: <20230714203802.GA3972960@hu-bjorande-lv.qualcomm.com> References: <20230714061010.15817-1-quic_ninanaik@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230714061010.15817-1-quic_ninanaik@quicinc.com> X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: km0LGNLvr1EcoYWenJ01xOVsmdjvxMLH X-Proofpoint-GUID: km0LGNLvr1EcoYWenJ01xOVsmdjvxMLH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-14_10,2023-07-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1011 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307140188 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 14, 2023 at 11:40:09AM +0530, Ninad Naik wrote: > SA8775 and newer target have added support for an increased number of > interrupt targets. To implement this change, the intr_target field, which > is used to configure the interrupt target in the interrupt configuration > register is increased from 3 bits to 4 bits. > > In accordance to these updates, a new intr_target_width member is > introduced in msm_pingroup structure. This member stores the value of > width of intr_target field in the interrupt configuration register. This > value is used to dynamically calculate and generate mask for setting the > intr_target field. By default, this mask is set to 3 bit wide, to ensure > backward compatibility with the older targets. > > Signed-off-by: Ninad Naik Very nice, Ninad. Reviewed-by: Bjorn Andersson > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 9 ++++++--- > drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ > drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 + > 3 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 2585ef2b2793..6ebcaa2220af 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -1038,6 +1038,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) > struct gpio_chip *gc = irq_data_get_irq_chip_data(d); > struct msm_pinctrl *pctrl = gpiochip_get_data(gc); > const struct msm_pingroup *g; > + u32 intr_target_mask = 0x7; I like Konrad's suggestion about making this GENMASK(2, 0). Please update that and include our R-b tags in v2. Regards, Bjorn