From: Yang Weijiang <weijiang.yang@intel.com>
To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org,
john.allen@amd.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: rick.p.edgecombe@intel.com, chao.gao@intel.com,
binbin.wu@linux.intel.com, weijiang.yang@intel.com,
Yu-cheng Yu <yu-cheng.yu@intel.com>,
Borislav Petkov <bp@alien8.de>, Kees Cook <keescook@chromium.org>,
Mike Rapoport <rppt@kernel.org>,
Pengfei Xu <pengfei.xu@intel.com>
Subject: [PATCH v4 01/20] x86/cpufeatures: Add CPU feature flags for shadow stacks
Date: Thu, 20 Jul 2023 23:03:33 -0400 [thread overview]
Message-ID: <20230721030352.72414-2-weijiang.yang@intel.com> (raw)
In-Reply-To: <20230721030352.72414-1-weijiang.yang@intel.com>
From: Rick Edgecombe <rick.p.edgecombe@intel.com>
The Control-Flow Enforcement Technology contains two related features,
one of which is Shadow Stacks. Future patches will utilize this feature
for shadow stack support in KVM, so add a CPU feature flags for Shadow
Stacks (CPUID.(EAX=7,ECX=0):ECX[bit 7]).
To protect shadow stack state from malicious modification, the registers
are only accessible in supervisor mode. This implementation
context-switches the registers with XSAVES. Make X86_FEATURE_SHSTK depend
on XSAVES.
The shadow stack feature, enumerated by the CPUID bit described above,
encompasses both supervisor and userspace support for shadow stack. In
near future patches, only userspace shadow stack will be enabled. In
expectation of future supervisor shadow stack support, create a software
CPU capability to enumerate kernel utilization of userspace shadow stack
support. This user shadow stack bit should depend on the HW "shstk"
capability and that logic will be implemented in future patches.
Co-developed-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mike Rapoport (IBM) <rppt@kernel.org>
Tested-by: Pengfei Xu <pengfei.xu@intel.com>
Tested-by: John Allen <john.allen@amd.com>
Tested-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/all/20230613001108.3040476-9-rick.p.edgecombe%40intel.com
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/disabled-features.h | 8 +++++++-
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index cb8ca46213be..d7215c8b7923 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -308,6 +308,7 @@
#define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
#define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */
#define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
+#define X86_FEATURE_USER_SHSTK (11*32+23) /* Shadow stack support for user mode applications */
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
@@ -380,6 +381,7 @@
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
#define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_SHSTK (16*32+ 7) /* "" Shadow stack */
#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
#define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */
diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
index fafe9be7a6f4..b9c7eae2e70f 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -105,6 +105,12 @@
# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31))
#endif
+#ifdef CONFIG_X86_USER_SHADOW_STACK
+#define DISABLE_USER_SHSTK 0
+#else
+#define DISABLE_USER_SHSTK (1 << (X86_FEATURE_USER_SHSTK & 31))
+#endif
+
/*
* Make sure to add features to the correct mask
*/
@@ -120,7 +126,7 @@
#define DISABLED_MASK9 (DISABLE_SGX)
#define DISABLED_MASK10 0
#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \
- DISABLE_CALL_DEPTH_TRACKING)
+ DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK)
#define DISABLED_MASK12 (DISABLE_LAM)
#define DISABLED_MASK13 0
#define DISABLED_MASK14 0
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index f6748c8bd647..e462c1d3800a 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -81,6 +81,7 @@ static const struct cpuid_dep cpuid_deps[] = {
{ X86_FEATURE_XFD, X86_FEATURE_XSAVES },
{ X86_FEATURE_XFD, X86_FEATURE_XGETBV1 },
{ X86_FEATURE_AMX_TILE, X86_FEATURE_XFD },
+ { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES },
{}
};
--
2.27.0
next prev parent reply other threads:[~2023-07-21 6:09 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 3:03 [PATCH v4 00/20] Enable CET Virtualization Yang Weijiang
2023-07-21 3:03 ` Yang Weijiang [this message]
2023-07-21 3:03 ` [PATCH v4 02/20] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 03/20] KVM:x86: Report XSS as to-be-saved if there are supported features Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 04/20] KVM:x86: Refresh CPUID on write to guest MSR_IA32_XSS Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 05/20] KVM:x86: Initialize kvm_caps.supported_xss Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 06/20] KVM:x86: Load guest FPU state when access XSAVE-managed MSRs Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 07/20] KVM:x86: Add fault checks for guest CR4.CET setting Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 08/20] KVM:x86: Report KVM supported CET MSRs as to-be-saved Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 09/20] KVM:x86: Add common code of CET MSR access Yang Weijiang
2023-07-26 7:33 ` Chao Gao
2023-07-26 8:26 ` Yang, Weijiang
2023-07-26 13:46 ` Chao Gao
2023-07-27 6:06 ` Yang, Weijiang
2023-07-27 7:41 ` Chao Gao
2023-07-27 16:58 ` Sean Christopherson
2023-07-21 3:03 ` [PATCH v4 10/20] KVM:x86: Make guest supervisor states as non-XSAVE managed Yang Weijiang
2023-07-24 8:26 ` Chao Gao
2023-07-24 13:50 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 11/20] KVM:x86: Save and reload GUEST_SSP to/from SMRAM Yang Weijiang
2023-07-24 9:13 ` Chao Gao
2023-07-24 14:16 ` Yang, Weijiang
2023-07-24 14:26 ` Sean Christopherson
2023-07-21 3:03 ` [PATCH v4 12/20] KVM:VMX: Introduce CET VMCS fields and control bits Yang Weijiang
2023-07-27 5:26 ` Chao Gao
2023-07-27 7:13 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 13/20] KVM:VMX: Emulate read and write to CET MSRs Yang Weijiang
2023-07-26 8:06 ` Chao Gao
2023-07-27 3:19 ` Yang, Weijiang
2023-07-27 5:16 ` Chao Gao
2023-07-27 7:10 ` Yang, Weijiang
2023-07-27 15:20 ` Sean Christopherson
2023-07-28 0:43 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 14/20] KVM:VMX: Set up interception for " Yang Weijiang
2023-07-26 8:30 ` Chao Gao
2023-07-27 3:48 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 15/20] KVM:VMX: Save host MSR_IA32_S_CET to VMCS field Yang Weijiang
2023-07-26 8:47 ` Chao Gao
2023-07-26 14:05 ` Sean Christopherson
2023-07-27 7:29 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 16/20] KVM:x86: Optimize CET supervisor SSP save/reload Yang Weijiang
2023-07-27 3:27 ` Chao Gao
2023-07-27 6:23 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 17/20] KVM:x86: Enable CET virtualization for VMX and advertise to userspace Yang Weijiang
2023-07-27 6:32 ` Chao Gao
2023-07-27 7:26 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 18/20] KVM:x86: Enable guest CET supervisor xstate bit support Yang Weijiang
2023-07-27 8:03 ` Chao Gao
2023-07-21 3:03 ` [PATCH v4 19/20] KVM:nVMX: Refine error code injection to nested VM Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 20/20] KVM:nVMX: Enable CET support for " Yang Weijiang
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