From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB2EC001B0 for ; Mon, 24 Jul 2023 01:41:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232160AbjGXBly (ORCPT ); Sun, 23 Jul 2023 21:41:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231137AbjGXBlC (ORCPT ); Sun, 23 Jul 2023 21:41:02 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBF1849C7; Sun, 23 Jul 2023 18:36:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 18D8160FC9; Mon, 24 Jul 2023 01:33:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1C76C433C9; Mon, 24 Jul 2023 01:32:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690162379; bh=zrYfDb9+nmxikItLD4r4B+NeH5bqoT98z7lmuBQ/6wc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RLNrPRfoBO0sMUxafkJleZL9/B1VsT1avJoEwzvORVo1hbB46nSmYR6HmzBMg5KzU fhzg0RyRdTG2ge8FgR5CI0SMvTjK35Phu6GFhUEiBqJPPgOZm5RTkW9Oy//KnMk1kW gzjK+B4a3MxYAwKxLTQmXL7jAGN0MiWAX8cUPddFioUWWCYJmKGWwUJ9n0ysDPnwgh EbQrZgA3pVc21sww0AajahsfaTgu8gKR/k+as+X3VTyZVDiBw3K04+83Pq0taOInEn ET0kXJEKNSeLEbxa1vLEAeJQgMm59wYJ1ilvcntt+HxFF7dCiBwJzdzcunXVona9zd lqRJz02j0rmEg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mika Westerberg , Pengfei Xu , Sasha Levin , andreas.noever@gmail.com, michael.jamet@intel.com, yehezkel.bernat@intel.com Subject: [PATCH AUTOSEL 6.1 15/34] thunderbolt: Add Intel Barlow Ridge PCI ID Date: Sun, 23 Jul 2023 21:32:18 -0400 Message-Id: <20230724013238.2329166-15-sashal@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230724013238.2329166-1-sashal@kernel.org> References: <20230724013238.2329166-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.40 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mika Westerberg [ Upstream commit 6f14a210661ce03988ef4ed3c8402037c8e06539 ] Intel Barlow Ridge is the first USB4 v2 controller from Intel. The controller exposes standard USB4 PCI class ID in typical configurations, however there is a way to configure it so that it uses a special class ID to allow using s different driver than the Windows inbox one. For this reason add the Barlow Ridge PCI ID to the Linux driver too so that the driver can attach regardless of the class ID. Tested-by: Pengfei Xu Signed-off-by: Mika Westerberg Signed-off-by: Sasha Levin --- drivers/thunderbolt/nhi.c | 2 ++ drivers/thunderbolt/nhi.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index 4a6a3802d7e51..288aaa05d0071 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -1479,6 +1479,8 @@ static struct pci_device_id nhi_ids[] = { .driver_data = (kernel_ulong_t)&icl_nhi_ops }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), .driver_data = (kernel_ulong_t)&icl_nhi_ops }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) }, /* Any USB4 compliant host */ { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h index b0718020c6f59..c15a0c46c9cff 100644 --- a/drivers/thunderbolt/nhi.h +++ b/drivers/thunderbolt/nhi.h @@ -75,6 +75,8 @@ extern const struct tb_nhi_ops icl_nhi_ops; #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef #define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e #define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d +#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x5781 +#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x5784 #define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2 #define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2 #define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3 -- 2.39.2