From: Yi Liu <yi.l.liu@intel.com>
To: joro@8bytes.org, alex.williamson@redhat.com, jgg@nvidia.com,
kevin.tian@intel.com, robin.murphy@arm.com,
baolu.lu@linux.intel.com
Cc: cohuck@redhat.com, eric.auger@redhat.com, nicolinc@nvidia.com,
kvm@vger.kernel.org, mjrosato@linux.ibm.com,
chao.p.peng@linux.intel.com, yi.l.liu@intel.com,
yi.y.sun@linux.intel.com, peterx@redhat.com, jasowang@redhat.com,
shameerali.kolothum.thodi@huawei.com, lulu@redhat.com,
suravee.suthikulpanit@amd.com, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
zhenzhong.duan@intel.com
Subject: [PATCH v4 07/12] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation
Date: Mon, 24 Jul 2023 04:13:29 -0700 [thread overview]
Message-ID: <20230724111335.107427-8-yi.l.liu@intel.com> (raw)
In-Reply-To: <20230724111335.107427-1-yi.l.liu@intel.com>
This adds the data structure for flushing iotlb for the nested domain
allocated with IOMMU_HWPT_TYPE_VTD_S1 type.
Cache invalidation path is performance path, so it's better to avoid
memory allocation in such path. To achieve it, this path reuses the
ucmd_buffer to copy user data. So the new data structures are added in
the ucmd_buffer union to avoid overflow.
This only supports invalidating IOTLB, but no for device-TLB as device-TLB
invalidation will be covered automatically in the IOTLB invalidation if the
underlying IOMMU driver has enabled ATS for the affected device.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
---
drivers/iommu/iommufd/main.c | 6 ++++
include/uapi/linux/iommufd.h | 58 ++++++++++++++++++++++++++++++++++++
2 files changed, 64 insertions(+)
diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c
index d49837397dfa..b927ace7f3af 100644
--- a/drivers/iommu/iommufd/main.c
+++ b/drivers/iommu/iommufd/main.c
@@ -485,6 +485,12 @@ union ucmd_buffer {
#ifdef CONFIG_IOMMUFD_TEST
struct iommu_test_cmd test;
#endif
+ /*
+ * hwpt_type specific structure used in the cache invalidation
+ * path.
+ */
+ struct iommu_hwpt_vtd_s1_invalidate vtd;
+ struct iommu_hwpt_vtd_s1_invalidate_desc req_vtd;
};
struct iommufd_ioctl_op {
diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h
index 90b0d3f603a7..2c1241448c87 100644
--- a/include/uapi/linux/iommufd.h
+++ b/include/uapi/linux/iommufd.h
@@ -523,6 +523,64 @@ struct iommu_resv_iova_ranges {
};
#define IOMMU_RESV_IOVA_RANGES _IO(IOMMUFD_TYPE, IOMMUFD_CMD_RESV_IOVA_RANGES)
+/**
+ * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
+ * stage-1 cache invalidation
+ * @IOMMU_VTD_QI_FLAGS_LEAF: The LEAF flag indicates whether only the
+ * leaf PTE caching needs to be invalidated
+ * and other paging structure caches can be
+ * preserved.
+ */
+enum iommu_hwpt_vtd_s1_invalidate_flags {
+ IOMMU_VTD_QI_FLAGS_LEAF = 1 << 0,
+};
+
+/**
+ * struct iommu_hwpt_vtd_s1_invalidate_desc - Intel VT-d stage-1 cache
+ * invalidation descriptor
+ * @addr: The start address of the addresses to be invalidated.
+ * @npages: Number of contiguous 4K pages to be invalidated.
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
+ * @__reserved: Must be 0
+ *
+ * The Intel VT-d specific invalidation data for user-managed stage-1 cache
+ * invalidation under nested translation. Userspace uses this structure to
+ * tell host about the impacted caches after modifying the stage-1 page table.
+ *
+ * Invalidating all the caches related to the hw_pagetable by setting @addr
+ * to be 0 and @npages to be __aligned_u64(-1).
+ */
+struct iommu_hwpt_vtd_s1_invalidate_desc {
+ __aligned_u64 addr;
+ __aligned_u64 npages;
+ __u32 flags;
+ __u32 __reserved;
+};
+
+/**
+ * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
+ * (IOMMU_HWPT_TYPE_VTD_S1)
+ * @flags: Must be 0
+ * @entry_size: Size in bytes of each cache invalidation request
+ * @entry_nr_uptr: User pointer to the number of invalidation requests.
+ * Kernel reads it to get the number of requests and
+ * updates the buffer with the number of requests that
+ * have been processed successfully. This pointer must
+ * point to a __u32 type of memory location.
+ * @inv_data_uptr: Pointer to the cache invalidation requests
+ *
+ * The Intel VT-d specific invalidation data for a set of cache invalidation
+ * requests. Kernel loops the requests one-by-one and stops when failure
+ * is encountered. The number of handled requests is reported to user by
+ * writing the buffer pointed by @entry_nr_uptr.
+ */
+struct iommu_hwpt_vtd_s1_invalidate {
+ __u32 flags;
+ __u32 entry_size;
+ __aligned_u64 entry_nr_uptr;
+ __aligned_u64 inv_data_uptr;
+};
+
/**
* struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
* @size: sizeof(struct iommu_hwpt_invalidate)
--
2.34.1
next prev parent reply other threads:[~2023-07-24 11:14 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-24 11:13 [PATCH v4 00/12] Add Intel VT-d nested translation Yi Liu
2023-07-24 11:13 ` [PATCH v4 01/12] iommufd: Add data structure for Intel VT-d stage-1 domain allocation Yi Liu
2023-08-02 6:40 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 02/12] iommu/vt-d: Extend dmar_domain to support nested domain Yi Liu
2023-08-02 6:42 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 03/12] iommu/vt-d: Add helper for nested domain allocation Yi Liu
2023-08-02 6:44 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 04/12] iommu/vt-d: Add helper to setup pasid nested translation Yi Liu
2023-08-02 7:10 ` Tian, Kevin
2023-08-02 8:09 ` Baolu Lu
2023-08-02 8:11 ` Baolu Lu
2023-08-02 8:13 ` Tian, Kevin
2023-08-03 3:13 ` Baolu Lu
2023-08-03 3:58 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 05/12] iommu/vt-d: Make domain attach helpers to be extern Yi Liu
2023-08-02 7:14 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 06/12] iommu/vt-d: Set the nested domain to a device Yi Liu
2023-08-02 7:22 ` Tian, Kevin
2023-08-03 3:17 ` Baolu Lu
2023-07-24 11:13 ` Yi Liu [this message]
2023-08-02 7:41 ` [PATCH v4 07/12] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation Tian, Kevin
2023-08-02 13:47 ` Jason Gunthorpe
2023-08-03 0:38 ` Tian, Kevin
2023-08-04 13:04 ` Liu, Yi L
2023-08-04 14:03 ` Jason Gunthorpe
2023-08-07 14:02 ` Liu, Yi L
2023-07-24 11:13 ` [PATCH v4 08/12] iommu/vt-d: Make iotlb flush helpers to be extern Yi Liu
2023-08-02 7:41 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 09/12] iommu/vt-d: Add iotlb flush for nested domain Yi Liu
2023-08-02 7:46 ` Tian, Kevin
2023-08-03 3:24 ` Baolu Lu
2023-08-03 4:00 ` Tian, Kevin
2023-08-03 4:05 ` Baolu Lu
2023-08-03 4:13 ` Tian, Kevin
2023-08-03 7:36 ` Baolu Lu
2023-08-07 15:08 ` Liu, Yi L
2023-08-08 3:12 ` Nicolin Chen
2023-08-08 12:34 ` Jason Gunthorpe
2023-08-08 17:41 ` Nicolin Chen
2023-08-09 8:22 ` Tian, Kevin
2023-08-09 8:50 ` Liu, Yi L
2023-08-09 8:58 ` Tian, Kevin
2023-08-09 9:30 ` Liu, Yi L
2023-08-09 16:24 ` Jason Gunthorpe
2023-08-09 19:12 ` Nicolin Chen
2023-08-09 19:19 ` Jason Gunthorpe
2023-08-09 20:17 ` Nicolin Chen
2023-08-10 2:49 ` Tian, Kevin
2023-08-10 15:57 ` Jason Gunthorpe
2023-08-10 17:14 ` Nicolin Chen
2023-08-10 19:27 ` Jason Gunthorpe
2023-08-10 21:02 ` Nicolin Chen
2023-08-11 3:52 ` Tian, Kevin
2023-08-11 16:45 ` Nicolin Chen
2023-08-15 6:18 ` Nicolin Chen
2023-08-18 16:56 ` Jason Gunthorpe
2023-08-18 17:56 ` Nicolin Chen
2023-08-18 18:20 ` Jason Gunthorpe
2023-08-18 18:25 ` Nicolin Chen
2023-08-21 1:24 ` Tian, Kevin
2023-08-10 3:28 ` Liu, Yi L
2023-08-10 3:33 ` Nicolin Chen
2023-07-24 11:13 ` [PATCH v4 10/12] iommu/vt-d: Add nested domain allocation Yi Liu
2023-08-02 7:47 ` Tian, Kevin
2023-07-24 11:13 ` [PATCH v4 11/12] iommu/vt-d: Implement hw_info for iommu capability query Yi Liu
2023-08-15 16:31 ` Jason Gunthorpe
2023-08-16 0:35 ` Baolu Lu
2023-08-16 1:10 ` Nicolin Chen
2023-08-16 11:46 ` Jason Gunthorpe
2023-08-16 11:48 ` Baolu Lu
2023-08-16 12:03 ` Liu, Yi L
2023-07-24 11:13 ` [PATCH v4 12/12] iommu/vt-d: Disallow nesting on domains with read-only mappings Yi Liu
2023-08-02 7:59 ` Tian, Kevin
2023-08-03 3:27 ` Baolu Lu
2023-08-03 4:00 ` Tian, Kevin
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