From: Charlie Jenkins <charlie@rivosinc.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
bpf@vger.kernel.org
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Peter Zijlstra" <peterz@infradead.org>,
"Josh Poimboeuf" <jpoimboe@kernel.org>,
"Jason Baron" <jbaron@akamai.com>,
"Steven Rostedt" <rostedt@goodmis.org>,
"Ard Biesheuvel" <ardb@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Alexei Starovoitov" <ast@kernel.org>,
"Daniel Borkmann" <daniel@iogearbox.net>,
"Andrii Nakryiko" <andrii@kernel.org>,
"Martin KaFai Lau" <martin.lau@linux.dev>,
"Song Liu" <song@kernel.org>, "Yonghong Song" <yhs@fb.com>,
"John Fastabend" <john.fastabend@gmail.com>,
"KP Singh" <kpsingh@kernel.org>,
"Stanislav Fomichev" <sdf@google.com>,
"Hao Luo" <haoluo@google.com>, "Jiri Olsa" <jolsa@kernel.org>,
"Björn Töpel" <bjorn@kernel.org>,
"Luke Nelson" <luke.r.nels@gmail.com>,
"Xi Wang" <xi.wang@gmail.com>, "Nam Cao" <namcaov@gmail.com>,
"Charlie Jenkins" <charlie@rivosinc.com>
Subject: [PATCH 07/10] RISC-V: nommu: Refactor instructions
Date: Thu, 03 Aug 2023 19:10:32 -0700 [thread overview]
Message-ID: <20230803-master-refactor-instructions-v4-v1-7-2128e61fa4ff@rivosinc.com> (raw)
In-Reply-To: <20230803-master-refactor-instructions-v4-v1-0-2128e61fa4ff@rivosinc.com>
Use shared instruction definitions in insn.h instead of manually
constructing them.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/kernel/traps_misaligned.c | 218 ++++++++---------------------------
1 file changed, 45 insertions(+), 173 deletions(-)
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 378f5b151443..b72045ce432a 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -12,144 +12,10 @@
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/csr.h>
+#include <asm/insn.h>
+#include <asm/reg.h>
-#define INSN_MATCH_LB 0x3
-#define INSN_MASK_LB 0x707f
-#define INSN_MATCH_LH 0x1003
-#define INSN_MASK_LH 0x707f
-#define INSN_MATCH_LW 0x2003
-#define INSN_MASK_LW 0x707f
-#define INSN_MATCH_LD 0x3003
-#define INSN_MASK_LD 0x707f
-#define INSN_MATCH_LBU 0x4003
-#define INSN_MASK_LBU 0x707f
-#define INSN_MATCH_LHU 0x5003
-#define INSN_MASK_LHU 0x707f
-#define INSN_MATCH_LWU 0x6003
-#define INSN_MASK_LWU 0x707f
-#define INSN_MATCH_SB 0x23
-#define INSN_MASK_SB 0x707f
-#define INSN_MATCH_SH 0x1023
-#define INSN_MASK_SH 0x707f
-#define INSN_MATCH_SW 0x2023
-#define INSN_MASK_SW 0x707f
-#define INSN_MATCH_SD 0x3023
-#define INSN_MASK_SD 0x707f
-
-#define INSN_MATCH_FLW 0x2007
-#define INSN_MASK_FLW 0x707f
-#define INSN_MATCH_FLD 0x3007
-#define INSN_MASK_FLD 0x707f
-#define INSN_MATCH_FLQ 0x4007
-#define INSN_MASK_FLQ 0x707f
-#define INSN_MATCH_FSW 0x2027
-#define INSN_MASK_FSW 0x707f
-#define INSN_MATCH_FSD 0x3027
-#define INSN_MASK_FSD 0x707f
-#define INSN_MATCH_FSQ 0x4027
-#define INSN_MASK_FSQ 0x707f
-
-#define INSN_MATCH_C_LD 0x6000
-#define INSN_MASK_C_LD 0xe003
-#define INSN_MATCH_C_SD 0xe000
-#define INSN_MASK_C_SD 0xe003
-#define INSN_MATCH_C_LW 0x4000
-#define INSN_MASK_C_LW 0xe003
-#define INSN_MATCH_C_SW 0xc000
-#define INSN_MASK_C_SW 0xe003
-#define INSN_MATCH_C_LDSP 0x6002
-#define INSN_MASK_C_LDSP 0xe003
-#define INSN_MATCH_C_SDSP 0xe002
-#define INSN_MASK_C_SDSP 0xe003
-#define INSN_MATCH_C_LWSP 0x4002
-#define INSN_MASK_C_LWSP 0xe003
-#define INSN_MATCH_C_SWSP 0xc002
-#define INSN_MASK_C_SWSP 0xe003
-
-#define INSN_MATCH_C_FLD 0x2000
-#define INSN_MASK_C_FLD 0xe003
-#define INSN_MATCH_C_FLW 0x6000
-#define INSN_MASK_C_FLW 0xe003
-#define INSN_MATCH_C_FSD 0xa000
-#define INSN_MASK_C_FSD 0xe003
-#define INSN_MATCH_C_FSW 0xe000
-#define INSN_MASK_C_FSW 0xe003
-#define INSN_MATCH_C_FLDSP 0x2002
-#define INSN_MASK_C_FLDSP 0xe003
-#define INSN_MATCH_C_FSDSP 0xa002
-#define INSN_MASK_C_FSDSP 0xe003
-#define INSN_MATCH_C_FLWSP 0x6002
-#define INSN_MASK_C_FLWSP 0xe003
-#define INSN_MATCH_C_FSWSP 0xe002
-#define INSN_MASK_C_FSWSP 0xe003
-
-#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
-
-#if defined(CONFIG_64BIT)
-#define LOG_REGBYTES 3
-#define XLEN 64
-#else
-#define LOG_REGBYTES 2
-#define XLEN 32
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-#define XLEN_MINUS_16 ((XLEN) - 16)
-
-#define SH_RD 7
-#define SH_RS1 15
-#define SH_RS2 20
-#define SH_RS2C 2
-
-#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
-#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
- (RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 1) << 6))
-#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 2) << 6))
-#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 2) << 6))
-#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 3) << 6))
-#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
- (RV_X(x, 7, 2) << 6))
-#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 7, 3) << 6))
-#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
-#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
-#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
-
-#define SHIFT_RIGHT(x, y) \
- ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
-
-#define REG_MASK \
- ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
-
-#define REG_OFFSET(insn, pos) \
- (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
-
-#define REG_PTR(insn, pos, regs) \
- (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
-
-#define GET_RM(insn) (((insn) >> 12) & 7)
-
-#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
-#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
-#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
-#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
-#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
-#define GET_SP(regs) (*REG_PTR(2, 0, regs))
-#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
-#define IMM_I(insn) ((s32)(insn) >> 20)
-#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
- (s32)(((insn) >> 7) & 0x1f))
-#define MASK_FUNCT3 0x7000
-
-#define GET_PRECISION(insn) (((insn) >> 25) & 3)
-#define GET_RM(insn) (((insn) >> 12) & 7)
-#define PRECISION_S 0
-#define PRECISION_D 1
+#define XLEN_MINUS_16 ((__riscv_xlen) - 16)
#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \
static inline type load_##type(const type *addr) \
@@ -245,58 +111,56 @@ int handle_misaligned_load(struct pt_regs *regs)
regs->epc = 0;
- if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
+ if (riscv_insn_is_lw(insn)) {
len = 4;
shift = 8 * (sizeof(unsigned long) - len);
#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
+ } else if (riscv_insn_is_ld(insn)) {
len = 8;
shift = 8 * (sizeof(unsigned long) - len);
- } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
+ } else if (riscv_insn_is_lwu(insn)) {
len = 4;
#endif
- } else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {
+ } else if (riscv_insn_is_fld(insn)) {
fp = 1;
len = 8;
- } else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {
+ } else if (riscv_insn_is_flw(insn)) {
fp = 1;
len = 4;
- } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
+ } else if (riscv_insn_is_lh(insn)) {
len = 2;
shift = 8 * (sizeof(unsigned long) - len);
- } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
+ } else if (riscv_insn_is_lhu(insn)) {
len = 2;
#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
+ } else if (riscv_insn_is_c_ld(insn)) {
len = 8;
shift = 8 * (sizeof(unsigned long) - len);
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ insn = riscv_insn_extract_csca_rs2(insn);
+ } else if (riscv_insn_is_c_ldsp(insn) && (RVC_RD_CI(insn))) {
len = 8;
shift = 8 * (sizeof(unsigned long) - len);
#endif
- } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
+ } else if (riscv_insn_is_c_lw(insn)) {
len = 4;
shift = 8 * (sizeof(unsigned long) - len);
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ insn = riscv_insn_extract_csca_rs2(insn);
+ } else if (riscv_insn_is_c_lwsp(insn) && (RVC_RD_CI(insn))) {
len = 4;
shift = 8 * (sizeof(unsigned long) - len);
- } else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {
+ } else if (riscv_insn_is_c_fld(insn)) {
fp = 1;
len = 8;
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {
+ insn = riscv_insn_extract_csca_rs2(insn);
+ } else if (riscv_insn_is_c_fldsp(insn)) {
fp = 1;
len = 8;
#if defined(CONFIG_32BIT)
- } else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {
+ } else if (riscv_insn_is_c_flw(insn)) {
fp = 1;
len = 4;
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {
+ insn = riscv_insn_extract_csca_rs2(insn);
+ } else if (riscv_insn_is_c_flwsp(insn)) {
fp = 1;
len = 4;
#endif
@@ -311,7 +175,8 @@ int handle_misaligned_load(struct pt_regs *regs)
if (fp)
return -1;
- SET_RD(insn, regs, val.data_ulong << shift >> shift);
+ rv_insn_reg_set_val((unsigned long *)regs, RV_EXTRACT_RD_REG(insn),
+ val.data_ulong << shift >> shift);
regs->epc = epc + INSN_LEN(insn);
@@ -328,32 +193,39 @@ int handle_misaligned_store(struct pt_regs *regs)
regs->epc = 0;
- val.data_ulong = GET_RS2(insn, regs);
+ rv_insn_reg_get_val((unsigned long *)regs, riscv_insn_extract_rs2(insn),
+ &val.data_ulong);
- if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
+ if (riscv_insn_is_sw(insn)) {
len = 4;
#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
+ } else if (riscv_insn_is_sd(insn)) {
len = 8;
#endif
- } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
+ } else if (riscv_insn_is_sh(insn)) {
len = 2;
#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
+ } else if (riscv_insn_is_c_sd(insn)) {
len = 8;
- val.data_ulong = GET_RS2S(insn, regs);
- } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rv_insn_reg_get_val((unsigned long *)regs,
+ riscv_insn_extract_cr_rs2(insn),
+ &val.data_ulong);
+ } else if (riscv_insn_is_c_sdsp(insn)) {
len = 8;
- val.data_ulong = GET_RS2C(insn, regs);
+ rv_insn_reg_get_val((unsigned long *)regs,
+ riscv_insn_extract_csca_rs2(insn),
+ &val.data_ulong);
#endif
- } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
+ } else if (riscv_insn_is_c_sw(insn)) {
len = 4;
- val.data_ulong = GET_RS2S(insn, regs);
- } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rv_insn_reg_get_val((unsigned long *)regs,
+ riscv_insn_extract_cr_rs2(insn),
+ &val.data_ulong);
+ } else if (riscv_insn_is_c_swsp(insn)) {
len = 4;
- val.data_ulong = GET_RS2C(insn, regs);
+ rv_insn_reg_get_val((unsigned long *)regs,
+ riscv_insn_extract_csca_rs2(insn),
+ &val.data_ulong);
} else {
regs->epc = epc;
return -1;
--
2.34.1
next prev parent reply other threads:[~2023-08-04 2:12 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-04 2:10 [PATCH 00/10] RISC-V: " Charlie Jenkins
2023-08-04 2:10 ` [PATCH 01/10] RISC-V: Expand instruction definitions Charlie Jenkins
2023-08-04 7:59 ` Conor Dooley
2023-08-04 17:26 ` Charlie Jenkins
2023-08-04 2:10 ` [PATCH 02/10] RISC-V: vector: Refactor instructions Charlie Jenkins
2023-08-04 2:10 ` [PATCH 03/10] RISC-V: Refactor jump label instructions Charlie Jenkins
2023-08-04 2:10 ` [PATCH 04/10] RISC-V: KGDB: Refactor instructions Charlie Jenkins
2023-08-04 2:10 ` [PATCH 05/10] RISC-V: module: " Charlie Jenkins
2023-08-04 2:10 ` [PATCH 06/10] RISC-V: Refactor patch instructions Charlie Jenkins
2023-08-04 2:10 ` Charlie Jenkins [this message]
2023-08-04 2:10 ` [PATCH 08/10] RISC-V: kvm: Refactor instructions Charlie Jenkins
2023-08-04 2:10 ` [PATCH 09/10] RISC-V: bpf: " Charlie Jenkins
2023-08-04 2:10 ` [PATCH 10/10] RISC-V: Refactor bug and traps instructions Charlie Jenkins
2023-08-04 5:16 ` kernel test robot
2023-08-04 9:28 ` [PATCH 00/10] RISC-V: Refactor instructions Andrew Jones
2023-08-04 17:24 ` Charlie Jenkins
2023-08-17 0:31 ` Charlie Jenkins
2023-08-17 3:57 ` Jessica Clarke
2023-08-17 4:05 ` Jessica Clarke
2023-08-17 16:43 ` Charlie Jenkins
2023-08-17 17:52 ` Palmer Dabbelt
2023-08-18 7:30 ` Andrew Jones
2023-09-06 18:51 ` Charlie Jenkins
2023-09-07 8:51 ` Andrew Jones
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