On Thu, Aug 03, 2023 at 09:24:24AM +0200, Michal Simek wrote:
> ZynqMP Cadence SPI IP core has own power domain that's why describe it as
> optional property.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.