From: Peter Zijlstra <peterz@infradead.org>
To: Xin Li <xin3.li@intel.com>
Cc: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H . Peter Anvin" <hpa@zytor.com>,
Juergen Gross <jgross@suse.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>
Subject: Re: [RFC PATCH 1/1] x86/traps: Get rid of exception handlers' second argument error code
Date: Fri, 4 Aug 2023 12:13:21 +0200 [thread overview]
Message-ID: <20230804101321.GH214207@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20230804075734.8372-1-xin3.li@intel.com>
On Fri, Aug 04, 2023 at 12:57:34AM -0700, Xin Li wrote:
> The IDT event delivery of X86_TRAP_DF, X86_TRAP_TS, X86_TRAP_NP,
> X86_TRAP_SS, X86_TRAP_GP, X86_TRAP_AC and X86_TRAP_CP pushes an error
> code into the orig_ax member of the pt_regs structure, and the error
> code is passed as the second argument of their C-handlers, although
> the pt_regs structure is already passed as the first argument.
>
> The asm entry code of such faults does the following
>
> movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
> movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
>
> to set the orig_ax member to -1 just before calling the C-handler.
>
> In addition, the IRQ entry code uses the second error code argument
> as its IRQ vector, as the IRQ asm entry code pushes its IRQ vector
> into the orig_ax member.
>
> The commit d99015b1abbad ("x86: move entry_64.S register saving out of
> the macros") introduced the changes to set orig_ax to -1, but I can't
> see why it's required. Our tests on x86_64 and x86_32 seem fine if
> orig_ax is left unchanged instead of set to -1.
That means that SYSCALL_NUM(regs) get to be garbage; or something like
that.
next prev parent reply other threads:[~2023-08-04 10:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-04 7:57 Xin Li
2023-08-04 10:13 ` Peter Zijlstra [this message]
2023-08-04 17:35 ` Li, Xin3
2023-08-04 19:01 ` Peter Zijlstra
2023-08-05 21:02 ` Thomas Gleixner
2023-08-04 10:25 ` Andrew Cooper
2023-08-04 10:35 ` Juergen Gross
2023-08-04 17:20 ` Li, Xin3
2023-08-04 17:19 ` Li, Xin3
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