From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
To: <linux-kernel@vger.kernel.org>, <robh+dt@kernel.org>,
<bhelgaas@google.com>, <krzysztof.kozlowski@linaro.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<conor+dt@kernel.org>
Cc: <lpieralisi@kernel.org>, <bharat.kumar.gogada@amd.com>,
<michal.simek@amd.com>, <linux-arm-kernel@lists.infradead.org>,
"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>
Subject: [PATCH v3 0/2] Increase ecam size value to discover 256 buses during
Date: Thu, 10 Aug 2023 17:50:00 +0530 [thread overview]
Message-ID: <20230810122002.133531-2-thippeswamy.havalige@amd.com> (raw)
In-Reply-To: <20230810122002.133531-1-thippeswamy.havalige@amd.com>
Current driver is supports up to 16 buses. The following code fixes
to support up to 256 buses.
update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
region to detect 256 buses.
Update ecam size to 256MB in device tree binding example.
Thippeswamy Havalige (2):
dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++----
2 files changed, 3 insertions(+), 5 deletions(-)
--
2.17.1
next prev parent reply other threads:[~2023-08-10 12:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-10 12:19 [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-08-10 12:20 ` Thippeswamy Havalige [this message]
2023-08-10 12:20 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-08-10 13:21 ` Rob Herring
2023-08-10 21:17 ` Rob Herring
2023-08-10 12:20 ` [PATCH v3 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
2023-08-10 21:17 ` Rob Herring
2023-08-11 5:07 ` Havalige, Thippeswamy
2023-08-11 16:51 ` Bjorn Helgaas
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