From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
To: <linux-kernel@vger.kernel.org>, <robh+dt@kernel.org>,
<bhelgaas@google.com>, <krzysztof.kozlowski@linaro.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<conor+dt@kernel.org>
Cc: <lpieralisi@kernel.org>, <bharat.kumar.gogada@amd.com>,
<michal.simek@amd.com>, <linux-arm-kernel@lists.infradead.org>,
"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>
Subject: [PATCH v4 0/3] Fix ecam size value to discover 256 buses during
Date: Mon, 14 Aug 2023 22:44:03 +0530 [thread overview]
Message-ID: <20230814171406.214932-2-thippeswamy.havalige@amd.com> (raw)
In-Reply-To: <20230814171406.214932-1-thippeswamy.havalige@amd.com>
Current driver is supports up to 16 buses. The following code fixes
to support up to 256 buses.
update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
region to detect 256 buses.
Update ecam size to 256MB in device tree binding example.
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++----
2 files changed, 3 insertions(+), 5 deletions(-)
--
2.17.1
next prev parent reply other threads:[~2023-08-14 17:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-14 17:14 [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-08-14 17:14 ` Thippeswamy Havalige [this message]
2023-08-14 17:14 ` [PATCH v4 1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-08-14 17:14 ` [PATCH v4 2/3] PCI: xilinx-nwl: Rename ECAM size default macro Thippeswamy Havalige
2023-08-14 17:14 ` [PATCH v4 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
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