From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
To: <linux-pci@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>
Cc: <bhelgaas@google.com>, <robh@kernel.org>, <kw@linux.com>,
<linux-kernel@vger.kernel.org>, <lpieralisi@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>
Subject: [PATCH v5 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
Date: Thu, 17 Aug 2023 17:40:44 +0530 [thread overview]
Message-ID: <20230817121044.8176-5-thippeswamy.havalige@amd.com> (raw)
In-Reply-To: <20230817121044.8176-1-thippeswamy.havalige@amd.com>
Our controller is expecting ECAM size to be programmed by software. By
programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB
ECAM region which is used to detect 16 buses, so by updating
"NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB
ECAM region to detect 256 buses.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
---
changes in v5:
None.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 8fe0e8a325b0..e307aceba5c9 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_MAX_SIZE 12
+#define NWL_ECAM_MAX_SIZE 16
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
--
2.25.1
prev parent reply other threads:[~2023-08-17 12:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 12:10 [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-08-17 12:10 ` [PATCH v5 0/3] Increase ecam size value to discover 256 buses during Thippeswamy Havalige
2023-08-17 12:10 ` [PATCH v5 1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-08-17 12:10 ` [PATCH v5 2/3] PCI: xilinx-nwl: Rename ECAM size default macro Thippeswamy Havalige
2023-08-17 12:10 ` Thippeswamy Havalige [this message]
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