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From: Zhifeng Tang <zhifeng.tang@unisoc.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Orson Zhai <orsonzhai@gmail.com>,
	Baolin Wang <baolin.wang@linux.alibaba.com>,
	Chunyan Zhang <zhang.lyra@gmail.com>,
	Zhifeng Tang <zhifeng.tang@unisoc.com>,
	Cixi Geng <cixi.geng1@unisoc.com>
Cc: <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Zhifeng Tang <zhifeng.tang23@gmail.com>,
	Wenming Wu <wenming.wu@unisoc.com>
Subject: [PATCH V2] clk: sprd: Fix thm_parents incorrect configuration
Date: Thu, 24 Aug 2023 15:29:18 +0800	[thread overview]
Message-ID: <20230824072918.7805-1-zhifeng.tang@unisoc.com> (raw)

The thm*_clk have two clock sources 32k and 250k,excluding 32m.

Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512")

---
V2: add Fixes tag.
---
Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
---
 drivers/clk/sprd/ums512-clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index fc25bdd85e4e..f43bb10bd5ae 100644
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
 			 0x250, 0, 3, UMS512_MUX_FLAG);
 
 static const struct clk_parent_data thm_parents[] = {
-	{ .fw_name = "ext-32m" },
+	{ .fw_name = "ext-32k" },
 	{ .hw = &clk_250k.hw  },
 };
 static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,
-- 
2.17.1


             reply	other threads:[~2023-08-24  7:32 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-24  7:29 Zhifeng Tang [this message]
2023-08-24  9:26 Zhifeng Tang
2023-09-11 20:31 ` Stephen Boyd

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