From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F9F7C83F17 for ; Mon, 28 Aug 2023 17:19:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232776AbjH1RTZ (ORCPT ); Mon, 28 Aug 2023 13:19:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbjH1RTE (ORCPT ); Mon, 28 Aug 2023 13:19:04 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7469BE1; Mon, 28 Aug 2023 10:19:02 -0700 (PDT) Received: from pendragon.ideasonboard.com (117.145-247-81.adsl-dyn.isp.belgacom.be [81.247.145.117]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 309135AA; Mon, 28 Aug 2023 19:17:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693243060; bh=yVdJKq+mPQjEPUJbQsM/4JUsxmp7xdIZUcCBV6dKcUM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=V+GGH2SYucP2Ci981tQg2Qk0hb9vW8q4soox170kuHwN/iAnkdBl/ZuvhRY7SnVPd mzj4R9Jjvvy6gGCWErXSons9HMYDdTlCT7V4+WWwzPemh9yfZIsgUfhEMLqeCwTmu9 2ztPXrNOuwTm+5f5CjCo1ftN569XTrNSiibo3KMg= Date: Mon, 28 Aug 2023 20:19:10 +0300 From: Laurent Pinchart To: Bryan O'Donoghue Cc: rfoss@kernel.org, todor.too@gmail.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, sakari.ailus@linux.intel.com, andrey.konovalov@linaro.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v2 7/9] media: qcom: camss: Fix invalid clock enable bit disjunction Message-ID: <20230828171910.GB14596@pendragon.ideasonboard.com> References: <20230822200626.1931129-1-bryan.odonoghue@linaro.org> <20230822200626.1931129-8-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20230822200626.1931129-8-bryan.odonoghue@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bryan, Thank you for the patch. On Tue, Aug 22, 2023 at 09:06:24PM +0100, Bryan O'Donoghue wrote: > define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) > > disjunction for gen2 ? BIT(7) : is a nop we are setting the same bit > either way. > > Fixes: 4abb21309fda ("media: camss: csiphy: Move to hardcode CSI Clock Lane number") > Cc: stable@vger.kernel.org > Signed-off-by: Bryan O'Donoghue > Reviewed-by: Konrad Dybcio Reviewed-by: Laurent Pinchart > --- > drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 04baa80494c66..4dba61b8d3f2a 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -476,7 +476,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, > > settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); > > - val = is_gen2 ? BIT(7) : CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > for (i = 0; i < c->num_data; i++) > val |= BIT(c->data[i].pos * 2); > > -- > 2.41.0 > -- Regards, Laurent Pinchart