From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 894D1C83F10 for ; Thu, 31 Aug 2023 11:48:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345578AbjHaLsz (ORCPT ); Thu, 31 Aug 2023 07:48:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231241AbjHaLsx (ORCPT ); Thu, 31 Aug 2023 07:48:53 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B0F9E45; Thu, 31 Aug 2023 04:48:48 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37VBmVxc079737; Thu, 31 Aug 2023 06:48:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1693482511; bh=rUzskDRuUxd5GNL1WaRYRS9VAZF5I2dFCZM8IxXPpiQ=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=rOi2LLyKwAAZeO1Hq8sxUNfIOH+JCEedPMvvwQS+DHP/XYmQcAuB+n5wAHvF35wyH WPHSy3j1+/F6zwXgQcH/N62hEy8+67pMHdH50wvG8am1jow3yq68dkn69b5pP0mArM rrTpomlnqNsYCGRX8JKghdVkqeq6PqjuaXcrWq8Y= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37VBmVCx123704 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 31 Aug 2023 06:48:31 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 31 Aug 2023 06:48:31 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 31 Aug 2023 06:48:30 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37VBmUm5013704; Thu, 31 Aug 2023 06:48:30 -0500 Date: Thu, 31 Aug 2023 06:48:30 -0500 From: Nishanth Menon To: Keerthy CC: , , , , , , , Subject: Re: [PATCH 4/5] arm64: dts: ti: k3-j721s2-main: Add main domain watchdog entries Message-ID: <20230831114830.oenlyvwyxbi2uerq@deserving> References: <20230830072622.19539-1-j-keerthy@ti.com> <20230830072622.19539-5-j-keerthy@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230830072622.19539-5-j-keerthy@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12:56-20230830, Keerthy wrote: > Add DT entries for main domain watchdog instances. > > Signed-off-by: Keerthy > --- > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index 87841bcc509d..33276d31faa1 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -1513,4 +1513,22 @@ > reg = <0x0 0x700000 0x0 0x1000>; > ti,esm-pins = <344>, <345>; > }; > + > + watchdog0: watchdog@2200000 { > + compatible = "ti,j7-rti-wdt"; > + reg = <0x0 0x2200000 0x0 0x100>; > + clocks = <&k3_clks 286 1>; > + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; > + assigned-clocks = <&k3_clks 286 1>; > + assigned-clock-parents = <&k3_clks 286 5>; > + }; > + > + watchdog1: watchdog@2210000 { > + compatible = "ti,j7-rti-wdt"; > + reg = <0x0 0x2210000 0x0 0x100>; > + clocks = <&k3_clks 287 1>; > + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; > + assigned-clocks = <&k3_clks 287 1>; > + assigned-clock-parents = <&k3_clks 287 5>; > + }; Are these all the wdts in main domain - do define and leave the other wdts disabled as they are tightly coupled to other processors (and must be enabled by the OS running on them), but defining them allows us to reuse the definitions in OSes running on R5s (for instance) to reuse the same device definitions. > }; > -- > 2.17.1 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D