From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <linux-riscv@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<conor.dooley@microchip.com>, <atishp@atishpatra.org>,
<anup@brainfault.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: <ajones@ventanamicro.com>, <heiko@sntech.de>,
<samuel@sholland.org>, <geert+renesas@glider.be>,
<n.shubin@yadro.com>, <dminus@andestech.com>,
<ycliang@andestech.com>, <tim609@andestech.com>,
<locus84@andestech.com>, <dylan@andestech.com>,
Yu Chien Peter Lin <peterlin@andestech.com>
Subject: [PATCH 0/4] Support Andes PMU extension
Date: Thu, 7 Sep 2023 10:16:31 +0800 [thread overview]
Message-ID: <20230907021635.1002738-1-peterlin@andestech.com> (raw)
This patch series introduces the Andes PMU errata, which
adds support for perf sampling and mode filtering with
the Andes PMU extension.
The custom PMU extension serves the same purpose as Sscofpmf.
Its non-standard local interrupt is assigned to bit 18 in the
custom S-mode local interrupt pending CSR (slip), while the
interrupt cause is (256 + 18).
This series is dependent on the series from Prabhakar,
- https://patchwork.kernel.org/project/linux-riscv/cover/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
The feature needs the PMU device callbacks in OpenSBI.
The OpenSBI and Linux patches can be found on Andes Technology GitHub
- https://github.com/andestech/opensbi/commits/andes-pmu-support
- https://github.com/andestech/linux/commits/andes-pmu-support
The PMU device tree node of AX45MP:
- https://github.com/andestech/opensbi/blob/andes-pmu-support/docs/pmu_support.md#example-3
Tested hardware:
- ASUS Tinker-V (RZ/Five, AX45MP single core)
- Andes AE350 (AX45MP quad core)
Locus Wei-Han Chen (1):
riscv: andes: Support symbolic FW and HW raw events
Yu Chien Peter Lin (3):
riscv: errata: Rename defines for Andes
irqchip/riscv-intc: Support large non-standard hwirq number
riscv: errata: Add Andes PMU errata
arch/riscv/Kconfig.errata | 13 ++
arch/riscv/errata/andes/errata.c | 55 +++++++-
arch/riscv/include/asm/errata_list.h | 45 ++++++-
arch/riscv/include/asm/vendorid_list.h | 2 +-
arch/riscv/kernel/alternative.c | 2 +-
drivers/irqchip/irq-riscv-intc.c | 10 +-
drivers/perf/riscv_pmu_sbi.c | 20 ++-
.../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++
.../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++
.../arch/riscv/andes/ax45/memory.json | 57 ++++++++
.../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
12 files changed, 453 insertions(+), 24 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
--
2.34.1
next reply other threads:[~2023-09-07 2:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 2:16 Yu Chien Peter Lin [this message]
2023-09-07 2:16 ` [PATCH 1/4] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-09-07 2:16 ` [RFC PATCH 2/4] irqchip/riscv-intc: Support large non-standard hwirq number Yu Chien Peter Lin
2023-09-07 10:22 ` Clément Léger
2023-09-11 8:04 ` Yu-Chien Peter Lin
2023-09-07 13:06 ` Anup Patel
2023-09-11 8:12 ` Yu-Chien Peter Lin
2023-09-07 2:16 ` [PATCH 3/4] riscv: errata: Add Andes PMU errata Yu Chien Peter Lin
2023-09-07 2:48 ` Samuel Holland
2023-09-11 2:38 ` Yu-Chien Peter Lin
2023-09-07 9:27 ` Conor Dooley
2023-09-07 11:02 ` Conor Dooley
2023-09-11 2:48 ` Yu-Chien Peter Lin
2023-09-11 12:35 ` Conor Dooley
2023-09-07 2:16 ` [PATCH 4/4] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
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