From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH 0/2] arm64/fp: Remove vector length pseudo registers
Date: Wed, 13 Sep 2023 15:48:11 +0100 [thread overview]
Message-ID: <20230913-arm64-vec-len-cpufeature-v1-0-cc69b0600a8a@kernel.org> (raw)
Since the pseudo registers used by the cpufeature code for the maximum
SVE and SME vector length appear to be unneeded other than as a double
check of the full vector length enumeration. As discussed when fixing
warnings from the pseudo register code let's simplify things by just
removing those registers and relying entirely on the full enumeration.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Mark Brown (2):
arm64/sve: Remove ZCR pseudo register from cpufeature code
arm64/sve: Remove SMCR pseudo register from cpufeature code
arch/arm64/include/asm/cpu.h | 6 ----
arch/arm64/include/asm/fpsimd.h | 1 -
arch/arm64/kernel/cpufeature.c | 58 ++++++-------------------------
arch/arm64/kernel/fpsimd.c | 75 +++++------------------------------------
4 files changed, 19 insertions(+), 121 deletions(-)
---
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
change-id: 20230912-arm64-vec-len-cpufeature-290d78e90422
Best regards,
--
Mark Brown <broonie@kernel.org>
next reply other threads:[~2023-09-13 14:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-13 14:48 Mark Brown [this message]
2023-09-13 14:48 ` [PATCH 1/2] arm64/sve: Remove ZCR pseudo register from cpufeature code Mark Brown
2023-09-13 14:48 ` [PATCH 2/2] arm64/sve: Remove SMCR " Mark Brown
2023-09-25 17:10 ` [PATCH 0/2] arm64/fp: Remove vector length pseudo registers Catalin Marinas
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