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From: Myunguk Kim <mwkim@gaonchips.com>
To: broonie@kernel.org
Cc: alsa-devel@alsa-project.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, fido_max@inbox.ru,
	joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org,
	kuninori.morimoto.gx@renesas.com, lgirdwood@gmail.com,
	linux-kernel@vger.kernel.org, mwkim@gaonchips.com,
	perex@perex.cz, robh+dt@kernel.org, tiwai@suse.com,
	u.kleine-koenig@pengutronix.de, xingyu.wu@starfivetech.com
Subject: Re: [PATCH] ASoC: dwc: Add Single DMA mode support
Date: Wed, 13 Sep 2023 13:09:03 +0900	[thread overview]
Message-ID: <20230913040902.1496711-1-mwkim@gaonchips.com> (raw)
In-Reply-To: <ZP8Irf6g+sG6Ax9j@finisterre.sirena.org.uk>

> This feels like something we ought to be discovering from the DMA API
> somehow, while it's not quite a property of the DMA controller (but
> rather of the SoC integration) in this case it could be a property of
> some DMA controller elsewhere and the whole process of finding and
> figuring out the properties of the DMA controler is handled by the DMA
> API.

In this case, it is not used through the DMA API. 
The connection relationship is as follows.
  i2s --- pcm_dmaengine ---  DMA IP (ie. pl330)
So, control was possible only by directly setting the maxburst property.

And, I will send v2 (separate code and bindings)

Thanks,
myunguk


  reply	other threads:[~2023-09-13  4:16 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-11  2:40 Myunguk Kim
2023-09-11  6:12 ` Krzysztof Kozlowski
2023-09-13  2:53   ` Myunguk Kim
2023-09-13  6:38     ` Krzysztof Kozlowski
2023-09-13  6:43       ` Myunguk Kim
2023-09-13  6:58         ` Krzysztof Kozlowski
2023-09-11 12:31 ` Mark Brown
2023-09-13  4:09   ` Myunguk Kim [this message]
2023-09-13 15:07     ` Mark Brown

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