From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C438EE6449 for ; Fri, 15 Sep 2023 08:45:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233108AbjIOIqA (ORCPT ); Fri, 15 Sep 2023 04:46:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233092AbjIOIpz (ORCPT ); Fri, 15 Sep 2023 04:45:55 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4852D2711 for ; Fri, 15 Sep 2023 01:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1694767549; x=1726303549; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; 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Fri, 15 Sep 2023 01:45:38 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Fri, 15 Sep 2023 01:45:33 -0700 Date: Fri, 15 Sep 2023 09:45:16 +0100 From: Conor Dooley To: Yong-Xuan Wang CC: , , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Guo Ren , Andrew Jones , wchen , Heiko Stuebner , Jisheng Zhang , Andrew Morton , Alexandre Ghiti , Kemeng Shi , David Hildenbrand , Sergey Matyukevich , "Matthew Wilcox (Oracle)" , Charlie Jenkins , Qinglin Pan , Rick Edgecombe , Evan Green , Sunil V L , Subject: Re: [PATCH 1/2] RISC-V: Detect and Enable Svadu Extension Support Message-ID: <20230915-triangle-fool-e7032469d3e1@wendy> References: <20230915082701.3643-1-yongxuan.wang@sifive.com> <20230915082701.3643-2-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="EjQ9rfLhfbgZuC1z" Content-Disposition: inline In-Reply-To: <20230915082701.3643-2-yongxuan.wang@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --EjQ9rfLhfbgZuC1z Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 15, 2023 at 08:26:57AM +0000, Yong-Xuan Wang wrote: > We detect Svadu extension support from DTB and add arch_has_hw_pte_young() > to enable optimization in MGLRU and __wp_page_copy_user() if Svadu > extension is available. >=20 > Signed-off-by: Jinyu Tang You're either missing a From: or a Co-developed-by: tag here. > Signed-off-by: Yong-Xuan Wang > --- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/pgtable.h | 6 ++++++ > arch/riscv/kernel/cpufeature.c | 1 + > 4 files changed, 9 insertions(+) >=20 > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 777cb8299551..10648b372a2a 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -194,6 +194,7 @@ > /* xENVCFG flags */ > #define ENVCFG_STCE (_AC(1, ULL) << 63) > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) > +#define ENVCFG_HADE (_AC(1, ULL) << 61) > #define ENVCFG_CBZE (_AC(1, UL) << 7) > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > #define ENVCFG_CBIE_SHIFT 4 > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwca= p.h > index b7b58258f6c7..1013661d6516 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -58,6 +58,7 @@ > #define RISCV_ISA_EXT_ZICSR 40 > #define RISCV_ISA_EXT_ZIFENCEI 41 > #define RISCV_ISA_EXT_ZIHPM 42 > +#define RISCV_ISA_EXT_SVADU 43 > =20 > #define RISCV_ISA_EXT_MAX 64 > =20 > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pg= table.h > index b2ba3f79cfe9..f3d077dff8ac 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t = _prot) > return __pgprot(prot); > } > =20 > +#define arch_has_hw_pte_young arch_has_hw_pte_young > +static inline bool arch_has_hw_pte_young(void) > +{ > + return riscv_has_extension_likely(RISCV_ISA_EXT_SVADU); No hardware currently has this, why is it likely? > +} > + > /* > * THP functions > */ > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur= e.c > index 1cfbba65d11a..ead378c04991 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), This needs to be documented in riscv/extensions.yaml. Thanks, Conor. > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > --=20 > 2.17.1 >=20 --EjQ9rfLhfbgZuC1z Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZQQZnAAKCRB4tDGHoIJi 0ve4AP9Q0ygRFHy474fh3DdhHwB/cWcWUvu2epcVNm3sD+D+vAD/ThRidAt4fJqZ 9lKQi1tz8nxCOaUKyukoH+PMnCRZrgw= =tV2Q -----END PGP SIGNATURE----- --EjQ9rfLhfbgZuC1z--