From: Conor Dooley <conor.dooley@microchip.com>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <david@redhat.com>,
<akpm@linux-foundation.org>, <alexghiti@rivosinc.com>,
<bjorn@rivosinc.com>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <ycliang@andestech.com>
Subject: Re: [PATCH v2 1/3] riscv: Improve PTDUMP to show RSW with non-zero value
Date: Mon, 18 Sep 2023 13:53:13 +0100 [thread overview]
Message-ID: <20230918-cassette-exclusion-b2ce53745a5c@wendy> (raw)
In-Reply-To: <20230914014027.273002-1-peterlin@andestech.com>
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On Thu, Sep 14, 2023 at 09:40:25AM +0800, Yu Chien Peter Lin wrote:
> + val = st->current_prot & pte_bits[i].mask;
> + if (val) {
> + if (pte_bits[i].mask == _PAGE_SOFT)
> + sprintf(s, pte_bits[i].set, val >> 8);
> + else
> + sprintf(s, "%s", pte_bits[i].set);
> + } else
> + sprintf(s, "%s", pte_bits[i].clear);
> +
just a nit, but checkpatch in the automation is whinging that you have
forgotten to add {} around both branches if this if statement.
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next prev parent reply other threads:[~2023-09-18 12:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 1:40 Yu Chien Peter Lin
2023-09-14 1:40 ` [PATCH v2 2/3] riscv: Introduce PBMT field to PTDUMP Yu Chien Peter Lin
2023-09-14 1:40 ` [PATCH v2 3/3] riscv: Introduce NAPOT " Yu Chien Peter Lin
2023-09-15 11:07 ` [PATCH v2 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Alexandre Ghiti
2023-09-16 7:22 ` Yu-Chien Peter Lin
2023-09-18 13:03 ` Alexandre Ghiti
2023-09-18 12:53 ` Conor Dooley [this message]
2023-09-20 3:17 ` Yu-Chien Peter Lin
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