From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2452DCE79AC for ; Wed, 20 Sep 2023 09:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234111AbjITJYh (ORCPT ); Wed, 20 Sep 2023 05:24:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234011AbjITJYZ (ORCPT ); Wed, 20 Sep 2023 05:24:25 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73FC5191 for ; Wed, 20 Sep 2023 02:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695201827; x=1726737827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fPbsFBLao1m6KO+ew1b44zTXvTcP/hWch9xcabu50YM=; b=OhPcdnxL1idRpEaftrk1+UlmB6q6HPZ6NJsRTtTq3lG0dEWEnmpNZn6B 5MstEzb+9IGFwsDR1OoDU67keaWRNPG3Tit6EgRqRqnGh1CDENUmSxMie FAegvyCCQ6Kpo0nGw6DiI1Kt1+W6/SukNd1Ysq2vfL7jdfrLxFTDBOrBO 94HXNFFUQkYwC3soUk1WOZ1A/93BFnb8tVHrOYgA+J+C2scb2pGrm/Jdm 95sdlBJmIKSEy26eNTGTykvy713nQzZv4NfPs3LZcVZDsUsLnW29cvgdM q0++/XR9t1W9TWe8nT20oqMNJY9BQ/7bh7g+7eHTxzeOKd0dnUyDm6Anu Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="444267597" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="444267597" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:23:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="781625271" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="781625271" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:23:44 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Lucas De Marchi , Daniele Ceraolo Spurio , Rodrigo Vivi Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] drm/xe/gsc: add HECI2 register offsets Date: Wed, 20 Sep 2023 12:19:20 +0300 Message-Id: <20230920091923.1573873-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920091923.1573873-1-alexander.usyskin@intel.com> References: <20230920091923.1573873-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vitaly Lubart Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h Reviewed-by: Rodrigo Vivi Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 39d7b0740bf0..4cbc3062cb9a 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -33,6 +33,10 @@ #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 + +#define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) -- 2.34.1