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([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:51 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 0/7] Add support to handle misaligned accesses in S-mode Date: Tue, 26 Sep 2023 17:03:09 +0200 Message-Id: <20230926150316.1129648-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture.") in the RISC-V ISA manual, it is stated that misaligned load/store might not be supported. However, the RISC-V kernel uABI describes that misaligned accesses are supported. In order to support that, this series adds support for S-mode handling of misaligned accesses as well support for prctl(PR_UNALIGN). Handling misaligned access in kernel allows for a finer grain control of the misaligned accesses behavior, and thanks to the prctl call, can allow disabling misaligned access emulation to generate SIGBUS. User space can then optimize its software by removing such access based on SIGBUS generation. Currently, this series is useful for people that uses a SBI that does not handled misaligned traps. In a near future, this series will make use a SBI extension [1] allowing to request delegation of the misaligned load/store traps to the S-mode software. This extension has been submitted for review to the riscv tech-prs group. An OpenSBI implementation for this spec is available at [2]. This series can be tested using the spike simulator [3] and an openSBI version [4] which allows to always delegate misaligned load/store to S-mode. [1] https://lists.riscv.org/g/tech-prs/message/540 [2] https://github.com/rivosinc/opensbi/tree/dev/cleger/fw_feature_upstream [3] https://github.com/riscv-software-src/riscv-isa-sim [4] https://github.com/rivosinc/opensbi/tree/dev/cleger/no_misaligned Clément Léger (7): riscv: remove unused functions in traps_misaligned.c riscv: add support for misaligned handling in S-mode riscv: report perf event for misaligned fault riscv: add floating point insn support to misaligned access emulation riscv: add support for sysctl unaligned_enabled control riscv: report misaligned accesses emulation to hwprobe riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN arch/riscv/Kconfig | 1 + arch/riscv/include/asm/cpufeature.h | 6 + arch/riscv/include/asm/entry-common.h | 3 + arch/riscv/include/asm/processor.h | 9 + arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/cpufeature.c | 6 +- arch/riscv/kernel/fpu.S | 117 ++++++++ arch/riscv/kernel/process.c | 18 ++ arch/riscv/kernel/setup.c | 1 + arch/riscv/kernel/traps.c | 9 - arch/riscv/kernel/traps_misaligned.c | 374 ++++++++++++++++++++++---- 11 files changed, 488 insertions(+), 58 deletions(-) -- 2.40.1