From: Alex Williamson <alex.williamson@redhat.com>
To: Bagas Sanjaya <bagasdotme@gmail.com>
Cc: <ankita@nvidia.com>, <jgg@nvidia.com>, <yishaih@nvidia.com>,
<shameerali.kolothum.thodi@huawei.com>, <kevin.tian@intel.com>,
<aniketa@nvidia.com>, <cjia@nvidia.com>, <kwankhede@nvidia.com>,
<targupta@nvidia.com>, <vsethi@nvidia.com>, <acurrid@nvidia.com>,
<apopple@nvidia.com>, <jhubbard@nvidia.com>, <danw@nvidia.com>,
<anuaggarwal@nvidia.com>, <dnigam@nvidia.com>,
<udhoke@nvidia.com>, <kvm@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v11 1/1] vfio/nvgpu: Add vfio pci variant module for grace hopper
Date: Mon, 9 Oct 2023 13:36:12 -0600 [thread overview]
Message-ID: <20231009133612.3fdd86a9.alex.williamson@redhat.com> (raw)
In-Reply-To: <ZSHykZ2GgSn0fE_x@debian.me>
On Sun, 8 Oct 2023 07:06:41 +0700
Bagas Sanjaya <bagasdotme@gmail.com> wrote:
> On Sun, Oct 08, 2023 at 01:52:54AM +0530, ankita@nvidia.com wrote:
> > PCI BAR are aligned to the power-of-2, but the actual memory on the
> > device may not. A read or write access to the physical address from the
> > last device PFN up to the next power-of-2 aligned physical address
> > results in reading ~0 and dropped writes.
> >
>
> Reading garbage or padding in that case?
>
> Confused...
The coherent memory size is rounded to a power-of-2 to be compliant with
PCI BAR semantics, but reading beyond the implemented size fills the
return buffer with -1 data, as is common on many platforms when reading
from an unimplemented section of the address space. Thanks,
Alex
next prev parent reply other threads:[~2023-10-09 19:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-07 20:22 ankita
2023-10-08 0:06 ` Bagas Sanjaya
2023-10-09 19:36 ` Alex Williamson [this message]
2023-10-11 5:45 ` Bagas Sanjaya
2023-10-10 8:42 ` Tian, Kevin
2023-10-10 11:33 ` Jason Gunthorpe
2023-10-11 2:00 ` Tian, Kevin
2023-10-11 12:00 ` Jason Gunthorpe
2023-10-13 3:43 ` Tian, Kevin
2023-10-13 4:35 ` Ankit Agrawal
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