From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58569CD80A4 for ; Tue, 10 Oct 2023 10:41:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbjJJKlg (ORCPT ); Tue, 10 Oct 2023 06:41:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbjJJKlc (ORCPT ); Tue, 10 Oct 2023 06:41:32 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E4D219E; Tue, 10 Oct 2023 03:41:30 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51FED1FB; Tue, 10 Oct 2023 03:42:11 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1DFA53F762; Tue, 10 Oct 2023 03:41:28 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, suzuki.poulose@arm.com Cc: James Clark , Catalin Marinas , Will Deacon , Jonathan Corbet , Russell King , Marc Zyngier , Oliver Upton , James Morse , Zenghui Yu , Mark Rutland , Zaid Al-Bassam , Geert Uytterhoeven , Reiji Watanabe , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Subject: [PATCH v2 0/3] arm64: perf: Add support for event counting threshold Date: Tue, 10 Oct 2023 11:40:26 +0100 Message-Id: <20231010104048.1923484-1-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v1: * Fix build on aarch32 by disabling FEAT_PMUv3_TH and splitting event type mask between the platforms * Change armv8pmu_write_evtype() to take unsigned long instead of u64 so it isn't unnecessarily wide on aarch32 * Add UL suffix to aarch64 event type mask definition ---- FEAT_PMUv3_TH (Armv8.8) is a new feature that allows conditional counting of PMU events depending on how much the event increments on a single cycle. Two new config fields for perf_event_open have been added, and a PMU cap file for reading the max_threshold. See the second commit message and the docs in the last commit for more details. The change has been validated on the Arm FVP model: # Zero values, works as expected (as before). $ perf stat -e dtlb_walk/threshold=0,threshold_control=0/ -- true 5962 dtlb_walk/threshold=0,threshold_control=0/ # Threshold >= 255 causes count to be 0 because dtlb_walk doesn't # increase by more than 1 per cycle. $ perf stat -e dtlb_walk/threshold=255,threshold_control=5/ -- true 0 dtlb_walk/threshold=255,threshold_control=5/ # Keeping comparison as >= but lowering the threshold to 1 makes the # count return. $ perf stat -e dtlb_walk/threshold=1,threshold_control=5/ -- true 6329 dtlb_walk/threshold=1,threshold_control=5/ James Clark (3): arm: perf: Include threshold control fields valid in PMEVTYPER mask arm64: perf: Add support for event counting threshold Documentation: arm64: Document the PMU event counting threshold feature Documentation/arch/arm64/perf.rst | 58 ++++++++++++++++++++++++++ arch/arm/include/asm/arm_pmuv3.h | 3 ++ arch/arm64/include/asm/arm_pmuv3.h | 4 ++ arch/arm64/kvm/pmu-emul.c | 1 + arch/arm64/kvm/sys_regs.c | 1 + drivers/perf/arm_pmuv3.c | 67 +++++++++++++++++++++++++++++- include/linux/perf/arm_pmuv3.h | 4 +- 7 files changed, 136 insertions(+), 2 deletions(-) base-commit: 94f6f0550c625fab1f373bb86a6669b45e9748b3 -- 2.34.1