From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB8A3CDB465 for ; Sat, 14 Oct 2023 09:28:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233029AbjJNJ25 (ORCPT ); Sat, 14 Oct 2023 05:28:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232957AbjJNJ2z (ORCPT ); Sat, 14 Oct 2023 05:28:55 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0911AD for ; Sat, 14 Oct 2023 02:28:54 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F6E6C433C8; Sat, 14 Oct 2023 09:28:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697275734; bh=ZpEO1IMYtH2irsHJdzCqFNZXRTOe6izWzOLePcvLYVQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bFcq0GjznydPaTONKjqfjV1+Nr7NZVwNPCQW5bLkxT1fQZovxY9n1S6AvO4BFzWuU TjR6cYOn61RQGer1aEsC4MPdJvFsGAslrjiZtzLUnGEUVNs91m9cmwvzq2qT5YNRcG l6zO8wCj9jejD8frT/V93xclYkS6S3IXunPiHuLvx2EL7DTPGOcqkrwE9GpJh3M1ZK bVFGRUI5GflYDnfCP5qrC+KThsY3q7iP4WZOoSlUM0lcAv1eUQc/UOZsCqUTEKyhVn hB0u8fypH9jkVxH2IVGTufXhjD17LMQI5jPHVb5xCgF+Hp2fDvLmB6JXCIV3gLeuV0 n+y2+d3E6cfAw== Date: Sat, 14 Oct 2023 10:28:49 +0100 From: Conor Dooley To: Jisheng Zhang Cc: Inochi Amaoto , Chao Wei , Chen Wang , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Message-ID: <20231014-scooter-blurred-995313b571ea@spud> References: <20231009112642.477337-1-inochiama@outlook.com> <20231013-catchable-wince-f24060feb639@spud> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="a/zpBNbMNsth1Q72" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --a/zpBNbMNsth1Q72 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline > Maybe this has been discussed before but I didn't find it. I'm wondering > the reason of adding each plic and clint binding for each SoC, can we > just use the thead,c900-plic for plic? > FWICT, arm gic dt usage follows this way, there's no binding for each SoC's > gic but directly use "arm,gic-v3" and so on. I'm not aware of why the gic-v3 is done like this, but having different compatibles allows differentiation between implementations/integrations of this interrupt controller. I think having that ability is especially helpful given T-Head have open-sourced a bunch of their IP. --a/zpBNbMNsth1Q72 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZSpfUQAKCRB4tDGHoIJi 0pX2AP4wYdW2thFcBTVUGxaO74xEyj4aQ1WBKWyE5D7v2uZ9JAEAkJn4LfRJBEGC c4In3tyIqVJS+5Y1dWIQO6WzcjO0tgk= =XuAN -----END PGP SIGNATURE----- --a/zpBNbMNsth1Q72--