From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <geert+renesas@glider.be>, <magnus.damm@gmail.com>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
<dylan@andestech.com>, <locus84@andestech.com>,
<dminus@andestech.com>,
"Yu Chien Peter Lin" <peterlin@andestech.com>
Subject: [PATCH v2 04/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
Date: Thu, 19 Oct 2023 21:58:10 +0800 [thread overview]
Message-ID: <20231019135810.3657665-1-peterlin@andestech.com> (raw)
The Andes INTC allows AX45MP cores to handle custom local
interrupts, such as the performance monitor overflow interrupt.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 8a726407fb76..a6345469e8c9 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -37,7 +37,7 @@ cpu0: cpu@0 {
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc";
interrupt-controller;
};
};
--
2.34.1
next reply other threads:[~2023-10-19 14:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 13:58 Yu Chien Peter Lin [this message]
2023-10-20 7:26 ` Geert Uytterhoeven
2023-10-20 8:17 ` Yu-Chien Peter Lin
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