From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D49C41513 for ; Thu, 19 Oct 2023 14:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345643AbjJSOCw (ORCPT ); Thu, 19 Oct 2023 10:02:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345856AbjJSOCt (ORCPT ); Thu, 19 Oct 2023 10:02:49 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D455013D for ; Thu, 19 Oct 2023 07:02:44 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39JE2DB1028894; Thu, 19 Oct 2023 22:02:13 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 19 Oct 2023 22:02:13 +0800 From: Yu Chien Peter Lin To: , , , , , , , , CC: , , , , , "Yu Chien Peter Lin" Subject: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller Date: Thu, 19 Oct 2023 21:59:05 +0800 Message-ID: <20231019135905.3658215-1-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39JE2DB1028894 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "andestech,cpu-intc" compatible string for Andes INTC which provides Andes-specific IRQ chip functions. Signed-off-by: Yu Chien Peter Lin --- Changes v1 -> v2: - New patch --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 97e8441eda1c..5b216e11c69f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -99,7 +99,9 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + enum: + - riscv,cpu-intc + - andestech,cpu-intc interrupt-controller: true -- 2.34.1