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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE37.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Fri, 20 Oct 2023 03:38:32 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 19 Oct 2023 22:38:31 -0500 From: Mario Limonciello To: , , , CC: , , , , , Mario Limonciello Subject: [PATCH 1/2] x86/apic: Allow reprogramming IOAPIC pins the first time for non-legacy IRQs Date: Thu, 19 Oct 2023 22:38:05 -0500 Message-ID: <20231020033806.88063-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|CH2PR12MB4118:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bac5145-6fe6-4f5d-c98e-08dbd11e087e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2023 03:38:32.3714 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bac5145-6fe6-4f5d-c98e-08dbd11e087e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the system is set up without legacy IRQs configured acpi_register_gsi_ioapic() still needs to be able to program the IOAPIC to match the values from _CRS which might not match what is already programmed to the IOAPIC. Reported-by: dlazar@gmail.com Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218003 Signed-off-by: Mario Limonciello --- arch/x86/kernel/apic/io_apic.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 00da6cf6b07d..27dd279dcc7b 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -928,12 +928,8 @@ static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) { struct mp_chip_data *data = irq_get_chip_data(irq); - /* - * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger - * and polarity attributes. So allow the first user to reprogram the - * pin with real trigger and polarity attributes. - */ - if (irq < nr_legacy_irqs() && data->count == 1) { + /* allow the first user to reprogram the pin with real trigger and polarity */ + if (data->count == 1) { if (info->ioapic.is_level != data->is_level) mp_register_handler(irq, info->ioapic.is_level); data->entry.is_level = data->is_level = info->ioapic.is_level; -- 2.34.1