From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B671C4332F for ; Wed, 1 Nov 2023 22:48:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347324AbjKAWsg (ORCPT ); Wed, 1 Nov 2023 18:48:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347343AbjKAWsa (ORCPT ); Wed, 1 Nov 2023 18:48:30 -0400 Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC430110 for ; Wed, 1 Nov 2023 15:48:18 -0700 (PDT) Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-3b2f507c03cso184402b6e.2 for ; Wed, 01 Nov 2023 15:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698878898; x=1699483698; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ed3AceHMZkBHW3Y7G0fWRXKUFOz+aro++Yp4kYAVXuk=; b=eWZTmUduVSomkhh3bkxKmV6Flq4imYMsrDpMo+CF1yIf3CGRKSjlY4K5gS+oU1fKhl OWM2tiSOKmluHLEQjSQyCgoDDUGuNT2FvFe2SGR0iBj03QuLOBzFang8DeLMR1CSI2y1 Cu/8FIta1Wau0NqbIbTysZFtDwbVJRl1i1pGvvLasuPpOgc0EJvqDDMeC2DHMhtYxokb OTRgP4E2IZohu5o4ufjU5KJJ9Dz0jDXoSlJDeZIKbCZPecTd8mqGd2ThIS0LXxOwRuwe heds4Vr7uDq9HLEY89KG4dLFIXjiWxLceV7wyLQ2DlTYU2TAetF/NzThM0is0kRwpDgL VNwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698878898; x=1699483698; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ed3AceHMZkBHW3Y7G0fWRXKUFOz+aro++Yp4kYAVXuk=; b=W/m9Ub178fGMHa47AokhpJMQ6wAYX7qKIpOjlSXHM2CT7k5vUuNOGIs49JjJEhWCSs FwA7q1z4dBr8pg3dqrOyMlgq6XleSwjePf4b0MQy6kTRTbQVuwcYNUZrChN4ON+c5G2D xLWbRSaZF76D8p1SxUcOqgQEDGppI2nVB0ov7BKFBwqcrfvznnpAdaJb3TFRh5n41h2S 4XIy88QvS48Uz/mfWd8E3Z3RjyxeEs1dBiW3S7hLBWjxU+oo0l5/gRICYDz1r8RASWth 0sRrbLWCfoPNEzgVGacjVXBMxAjLB4i9+vq7qyq+cSWGFnsqK93RUSlg2kx2/+89Ae1R agWQ== X-Gm-Message-State: AOJu0YwNL6pFAbl15SB4LC0iGLdvRLLb5YfML8PDfo9vr1NPvfk66tOg WDjh6HVFPbBJq+6lrJueE1Qzzw== X-Google-Smtp-Source: AGHT+IHopUzoXmnmWd14ia19E+/4HILvhDaQ9lTPnrMCLKpAh1AzG9vNZBvySp5as5cAaQjvBxPEhQ== X-Received: by 2002:a05:6808:1920:b0:3b5:64c9:5146 with SMTP id bf32-20020a056808192000b003b564c95146mr7234179oib.42.1698878898191; Wed, 01 Nov 2023 15:48:18 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id be24-20020a056808219800b003b274008e46sm376580oib.0.2023.11.01.15.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 15:48:17 -0700 (PDT) From: Charlie Jenkins Date: Wed, 01 Nov 2023 15:48:13 -0700 Subject: [PATCH v10 3/5] riscv: Checksum header MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20231101-optimize_checksum-v10-3-a498577bb969@rivosinc.com> References: <20231101-optimize_checksum-v10-0-a498577bb969@rivosinc.com> In-Reply-To: <20231101-optimize_checksum-v10-0-a498577bb969@rivosinc.com> To: Charlie Jenkins , Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , Xiao Wang , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Cc: Paul Walmsley , Albert Ou , Arnd Bergmann , Conor Dooley X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provide checksum algorithms that have been designed to leverage riscv instructions such as rotate. In 64-bit, can take advantage of the larger register to avoid some overflow checking. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley --- arch/riscv/include/asm/checksum.h | 81 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h new file mode 100644 index 000000000000..3d77cac338fe --- /dev/null +++ b/arch/riscv/include/asm/checksum.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Checksum routines + * + * Copyright (C) 2023 Rivos Inc. + */ +#ifndef __ASM_RISCV_CHECKSUM_H +#define __ASM_RISCV_CHECKSUM_H + +#include +#include + +#define ip_fast_csum ip_fast_csum + +/* Define riscv versions of functions before importing asm-generic/checksum.h */ +#include + +/* + * Quickly compute an IP checksum with the assumption that IPv4 headers will + * always be in multiples of 32-bits, and have an ihl of at least 5. + * @ihl is the number of 32 bit segments and must be greater than or equal to 5. + * @iph is assumed to be word aligned given that NET_IP_ALIGN is set to 2 on + * riscv, defining IP headers to be aligned. + */ +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + unsigned long csum = 0; + int pos = 0; + + do { + csum += ((const unsigned int *)iph)[pos]; + if (IS_ENABLED(CONFIG_32BIT)) + csum += csum < ((const unsigned int *)iph)[pos]; + } while (++pos < ihl); + + /* + * ZBB only saves three instructions on 32-bit and five on 64-bit so not + * worth checking if supported without Alternatives. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + unsigned long fold_temp; + + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, + RISCV_ISA_EXT_ZBB, 1) + : + : + : + : no_zbb); + + if (IS_ENABLED(CONFIG_32BIT)) { + asm(".option push \n\ + .option arch,+zbb \n\ + not %[fold_temp], %[csum] \n\ + rori %[csum], %[csum], 16 \n\ + sub %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); + } else { + asm(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 32 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + not %[fold_temp], %[csum] \n\ + roriw %[csum], %[csum], 16 \n\ + subw %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); + } + return csum >> 16; + } +no_zbb: +#ifndef CONFIG_32BIT + csum += ror64(csum, 32); + csum >>= 32; +#endif + return csum_fold((__force __wsum)csum); +} + +#endif /* __ASM_RISCV_CHECKSUM_H */ -- 2.34.1