From: Ravi Bangoria <ravi.bangoria@amd.com>
To: <acme@kernel.org>, <namhyung@kernel.org>
Cc: <ravi.bangoria@amd.com>, <kim.phillips@amd.com>,
<peterz@infradead.org>, <mingo@redhat.com>,
<mark.rutland@arm.com>, <alexander.shishkin@linux.intel.com>,
<jolsa@kernel.org>, <irogers@google.com>,
<adrian.hunter@intel.com>, <kan.liang@linux.intel.com>,
<changbin.du@huawei.com>, <yangjihong1@huawei.com>,
<zwisler@chromium.org>, <wangming01@loongson.cn>,
<chenhuacai@kernel.org>, <kprateek.nayak@amd.com>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <sandipan.das@amd.com>,
<ananth.narayan@amd.com>, <santosh.shukla@amd.com>
Subject: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default event on certain Zen2 processors
Date: Tue, 7 Nov 2023 14:03:30 +0530 [thread overview]
Message-ID: <20231107083331.901-1-ravi.bangoria@amd.com> (raw)
By default, Perf uses precise cycles event when no explicit event is
specified by user. Precise cycles event is forwarded to ibs_op// pmu
on AMD. However, IBS has hw issue on certain Zen2 processors where
it might raise NMI without sample_valid bit set, which causes Unknown
NMI warnings. (Erratum #1215: IBS (Instruction Based Sampling) Counter
Valid Value May be Incorrect After Exit From Core C6 (CC6) State.) So,
use non-precise cycles as default event on affected processors.
This does not prevent user to use explicit precise cycles event or
ibs_op// pmu directly.
Suggested-by: Arnaldo Carvalho de Melo <acme@kernel.org>
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
---
tools/perf/arch/x86/util/evlist.c | 34 +++++++++++++++++++++++++++++++
tools/perf/builtin-record.c | 2 +-
tools/perf/builtin-top.c | 2 +-
tools/perf/util/evlist.c | 12 ++++++++++-
tools/perf/util/evlist.h | 2 ++
5 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/evlist.c
index b1ce0c52d88d..f4478179c91b 100644
--- a/tools/perf/arch/x86/util/evlist.c
+++ b/tools/perf/arch/x86/util/evlist.c
@@ -5,6 +5,8 @@
#include "util/evlist.h"
#include "util/parse-events.h"
#include "util/event.h"
+#include "util/env.h"
+#include "linux/string.h"
#include "topdown.h"
#include "evsel.h"
@@ -92,3 +94,35 @@ int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs)
/* Default ordering by insertion index. */
return lhs->core.idx - rhs->core.idx;
}
+
+/*
+ * Precise cycles event is forwarded to ibs_op// pmu on AMD. However, IBS
+ * has hw issue on certain Zen2 processors where it might raise NMI without
+ * sample_valid bit set, which causes Unknown NMI warnings. So default to
+ * non-precise cycles event on affected processors.
+ */
+const char *arch_evlist__default_cycles_event(bool can_profile_kernel)
+{
+ struct perf_env env = { .total_mem = 0, };
+ unsigned int family, model, stepping;
+ bool is_amd;
+ int ret;
+
+ perf_env__cpuid(&env);
+ is_amd = env.cpuid && strstarts(env.cpuid, "AuthenticAMD");
+ if (!is_amd)
+ goto out;
+
+ ret = sscanf(env.cpuid, "%*[^,],%u,%u,%u", &family, &model, &stepping);
+ if (ret == 3 && family == 0x17 && (
+ (model >= 0x30 && model <= 0x3f) ||
+ (model >= 0x60 && model <= 0x7f) ||
+ (model >= 0x90 && model <= 0x9f))) {
+ perf_env__exit(&env);
+ return can_profile_kernel ? "cycles" : "cycles:u";
+ }
+
+out:
+ perf_env__exit(&env);
+ return can_profile_kernel ? "cycles:P" : "cycles:Pu";
+}
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index dcf288a4fb9a..e58d8ac8a77b 100644
--- a/tools/perf/builtin-record.c
+++ b/tools/perf/builtin-record.c
@@ -4150,7 +4150,7 @@ int cmd_record(int argc, const char **argv)
if (rec->evlist->core.nr_entries == 0) {
bool can_profile_kernel = perf_event_paranoid_check(1);
- err = parse_event(rec->evlist, can_profile_kernel ? "cycles:P" : "cycles:Pu");
+ err = parse_event(rec->evlist, evlist__default_cycles_event(can_profile_kernel));
if (err)
goto out;
}
diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c
index ea8c7eca5eee..21368421eddd 100644
--- a/tools/perf/builtin-top.c
+++ b/tools/perf/builtin-top.c
@@ -1666,7 +1666,7 @@ int cmd_top(int argc, const char **argv)
if (!top.evlist->core.nr_entries) {
bool can_profile_kernel = perf_event_paranoid_check(1);
- int err = parse_event(top.evlist, can_profile_kernel ? "cycles:P" : "cycles:Pu");
+ int err = parse_event(top.evlist, evlist__default_cycles_event(can_profile_kernel));
if (err)
goto out_delete_evlist;
diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c
index e36da58522ef..406ed851cafc 100644
--- a/tools/perf/util/evlist.c
+++ b/tools/perf/util/evlist.c
@@ -90,6 +90,16 @@ struct evlist *evlist__new(void)
return evlist;
}
+const char * __weak arch_evlist__default_cycles_event(bool can_profile_kernel)
+{
+ return can_profile_kernel ? "cycles:P" : "cycles:Pu";
+}
+
+const char *evlist__default_cycles_event(bool can_profile_kernel)
+{
+ return arch_evlist__default_cycles_event(can_profile_kernel);
+}
+
struct evlist *evlist__new_default(void)
{
struct evlist *evlist = evlist__new();
@@ -100,7 +110,7 @@ struct evlist *evlist__new_default(void)
return NULL;
can_profile_kernel = perf_event_paranoid_check(1);
- err = parse_event(evlist, can_profile_kernel ? "cycles:P" : "cycles:Pu");
+ err = parse_event(evlist, evlist__default_cycles_event(can_profile_kernel));
if (err) {
evlist__delete(evlist);
evlist = NULL;
diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h
index 98e7ddb2bd30..7267b4fb1981 100644
--- a/tools/perf/util/evlist.h
+++ b/tools/perf/util/evlist.h
@@ -91,6 +91,8 @@ struct evsel_str_handler {
struct evlist *evlist__new(void);
struct evlist *evlist__new_default(void);
+const char *arch_evlist__default_cycles_event(bool can_profile_kernel);
+const char *evlist__default_cycles_event(bool can_profile_kernel);
struct evlist *evlist__new_dummy(void);
void evlist__init(struct evlist *evlist, struct perf_cpu_map *cpus,
struct perf_thread_map *threads);
--
2.41.0
next reply other threads:[~2023-11-07 8:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-07 8:33 Ravi Bangoria [this message]
2023-11-07 8:33 ` [PATCH 2/2] perf header: Additional note on AMD IBS for max_precise pmu cap Ravi Bangoria
2023-11-09 19:56 ` Arnaldo Carvalho de Melo
2023-11-07 18:22 ` [PATCH 1/2] perf tool AMD: Use non-precise cycles as default event on certain Zen2 processors Ian Rogers
2023-11-10 9:37 ` Ravi Bangoria
2023-11-09 21:53 ` Namhyung Kim
2023-11-10 9:46 ` Ravi Bangoria
2023-12-08 23:33 ` Namhyung Kim
2023-12-11 13:53 ` Ravi Bangoria
2023-12-11 23:01 ` Namhyung Kim
2023-12-12 4:18 ` Ravi Bangoria
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231107083331.901-1-ravi.bangoria@amd.com \
--to=ravi.bangoria@amd.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=ananth.narayan@amd.com \
--cc=changbin.du@huawei.com \
--cc=chenhuacai@kernel.org \
--cc=irogers@google.com \
--cc=jolsa@kernel.org \
--cc=kan.liang@linux.intel.com \
--cc=kim.phillips@amd.com \
--cc=kprateek.nayak@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=sandipan.das@amd.com \
--cc=santosh.shukla@amd.com \
--cc=wangming01@loongson.cn \
--cc=yangjihong1@huawei.com \
--cc=zwisler@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®