From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will@kernel.org,
catalin.marinas@arm.com, mark.rutland@arm.com
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Mark Brown <broonie@kernel.org>,
James Clark <james.clark@arm.com>, Rob Herring <robh@kernel.org>,
Marc Zyngier <maz@kernel.org>,
Suzuki Poulose <suzuki.poulose@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
linux-perf-users@vger.kernel.org,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
kvmarm@lists.linux.dev
Subject: [V14 2/8] KVM: arm64: Prevent guest accesses into BRBE system registers/instructions
Date: Tue, 14 Nov 2023 10:43:23 +0530 [thread overview]
Message-ID: <20231114051329.327572-3-anshuman.khandual@arm.com> (raw)
In-Reply-To: <20231114051329.327572-1-anshuman.khandual@arm.com>
Currently BRBE feature is not supported in a guest environment. This hides
BRBE feature availability via masking ID_AA64DFR0_EL1.BRBE field. This also
blocks guest accesses into BRBE system registers and instructions as if the
underlying hardware never implemented FEAT_BRBE feature.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: kvmarm@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V14:
- This is a new patch in the series
arch/arm64/kvm/sys_regs.c | 130 ++++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 4735e1b37fb3..42701065b3cd 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1583,6 +1583,9 @@ static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
/* Hide SPE from guests */
val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
+ /* Hide BRBE from guests */
+ val &= ~ID_AA64DFR0_EL1_BRBE_MASK;
+
return val;
}
@@ -2042,6 +2045,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_DC_CISW), access_dcsw },
{ SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
{ SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
+ { SYS_DESC(OP_BRB_IALL), undef_access },
+ { SYS_DESC(OP_BRB_INJ), undef_access },
DBG_BCR_BVR_WCR_WVR_EL1(0),
DBG_BCR_BVR_WCR_WVR_EL1(1),
@@ -2072,6 +2077,131 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
{ SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
+ /*
+ * BRBE branch record sysreg address space is interleaved between
+ * corresponding BRBINF<N>_EL1, BRBSRC<N>_EL1, and BRBTGT<N>_EL1.
+ */
+ { SYS_DESC(SYS_BRBINF0_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC0_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT0_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF16_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC16_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT16_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF1_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC1_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT1_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF17_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC17_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT17_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF2_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC2_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT2_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF18_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC18_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT18_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF3_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC3_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT3_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF19_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC19_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT19_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF4_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC4_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT4_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF20_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC20_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT20_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF5_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC5_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT5_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF21_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC21_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT21_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF6_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC6_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT6_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF22_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC22_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT22_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF7_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC7_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT7_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF23_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC23_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT23_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF8_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC8_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT8_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF24_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC24_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT24_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF9_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC9_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT9_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF25_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC25_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT25_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF10_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC10_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT10_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF26_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC26_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT26_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF11_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC11_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT11_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF27_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC27_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT27_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF12_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC12_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT12_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF28_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC28_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT28_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF13_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC13_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT13_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF29_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC29_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT29_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF14_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC14_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT14_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF30_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC30_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT30_EL1), undef_access },
+
+ { SYS_DESC(SYS_BRBINF15_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC15_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT15_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINF31_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRC31_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGT31_EL1), undef_access },
+
+ /* Remaining BRBE sysreg addresses space */
+ { SYS_DESC(SYS_BRBCR_EL1), undef_access },
+ { SYS_DESC(SYS_BRBFCR_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTS_EL1), undef_access },
+ { SYS_DESC(SYS_BRBINFINJ_EL1), undef_access },
+ { SYS_DESC(SYS_BRBSRCINJ_EL1), undef_access },
+ { SYS_DESC(SYS_BRBTGTINJ_EL1), undef_access },
+ { SYS_DESC(SYS_BRBIDR0_EL1), undef_access },
+
{ SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
{ SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
// DBGDTR[TR]X_EL0 share the same encoding
--
2.25.1
next prev parent reply other threads:[~2023-11-14 5:14 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 5:13 [V14 0/8] arm64/perf: Enable branch stack sampling Anshuman Khandual
2023-11-14 5:13 ` [V14 1/8] arm64/sysreg: Add BRBE registers and fields Anshuman Khandual
2023-11-14 5:13 ` Anshuman Khandual [this message]
2023-11-14 5:13 ` [V14 3/8] drivers: perf: arm_pmuv3: Enable branch stack sampling framework Anshuman Khandual
2023-11-14 9:58 ` James Clark
2023-11-15 5:44 ` Anshuman Khandual
2023-11-15 9:37 ` James Clark
2023-11-21 9:13 ` Anshuman Khandual
2023-11-14 12:14 ` James Clark
2023-11-15 7:22 ` Anshuman Khandual
2023-11-15 10:07 ` James Clark
2023-11-21 9:57 ` Anshuman Khandual
2023-11-23 12:35 ` James Clark
2023-11-27 8:06 ` Anshuman Khandual
2023-11-14 17:10 ` James Clark
2023-11-30 3:58 ` Anshuman Khandual
2023-11-14 5:13 ` [V14 4/8] drivers: perf: arm_pmuv3: Enable branch stack sampling via FEAT_BRBE Anshuman Khandual
2023-11-14 12:11 ` James Clark
2023-11-21 10:47 ` Anshuman Khandual
2023-11-14 5:13 ` [V14 5/8] KVM: arm64: nvhe: Disable branch generation in nVHE guests Anshuman Khandual
2023-11-14 9:16 ` James Clark
2023-11-21 11:12 ` Anshuman Khandual
2023-11-23 13:54 ` James Clark
2023-11-27 8:25 ` Anshuman Khandual
2023-11-14 5:13 ` [V14 6/8] perf: test: Speed up running brstack test on an Arm model Anshuman Khandual
2023-11-14 5:13 ` [V14 7/8] perf: test: Remove empty lines from branch filter test output Anshuman Khandual
2023-11-14 5:13 ` [V14 8/8] perf: test: Extend branch stack sampling test for Arm64 BRBE Anshuman Khandual
2023-11-14 17:17 ` [V14 0/8] arm64/perf: Enable branch stack sampling James Clark
2023-11-22 5:15 ` Anshuman Khandual
2023-11-23 16:23 ` James Clark
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