From: "Clément Léger" <cleger@rivosinc.com>
To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Palmer Dabbelt" <palmer@rivosinc.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Jonathan Corbet" <corbet@lwn.net>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Evan Green" <evan@rivosinc.com>,
"Conor Dooley" <conor@kernel.org>,
"Samuel Ortiz" <sameo@rivosinc.com>,
"Jerry Shih" <jerry.shih@sifive.com>
Subject: [PATCH v4 10/20] riscv: hwprobe: export Zfh[min] ISA extensions
Date: Tue, 14 Nov 2023 09:12:46 -0500 [thread overview]
Message-ID: <20231114141256.126749-11-cleger@rivosinc.com> (raw)
In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com>
Export Zfh[min] ISA extensions[1] through hwprobe only if FPU support
is available.
Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
Documentation/arch/riscv/hwprobe.rst | 6 ++++++
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_riscv.c | 5 +++++
3 files changed, 13 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index a08fcd899b6d..397d53195f49 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -140,6 +140,12 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
+ as defined in the RISC-V ISA manual.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
+ supported as defined in the RISC-V ISA manual.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 89628a76ca04..2d960777ea43 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -50,6 +50,8 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
+#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 9bbcd7334d96..d776c6c39fcd 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -186,6 +186,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZVKSH);
EXT_KEY(ZVKT);
}
+
+ if (has_fpu()) {
+ EXT_KEY(ZFH);
+ EXT_KEY(ZFHMIN);
+ }
#undef EXT_KEY
}
--
2.42.0
next prev parent reply other threads:[~2023-11-14 14:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
2023-11-14 14:12 ` [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Clément Léger
2023-11-14 14:12 ` [PATCH v4 02/20] riscv: hwprobe: export missing Zbc ISA extension Clément Léger
2023-11-14 14:12 ` [PATCH v4 03/20] riscv: add ISA extension parsing for scalar crypto Clément Léger
2023-11-14 14:12 ` [PATCH v4 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Clément Léger
2023-11-22 16:13 ` Conor Dooley
2023-11-14 14:12 ` [PATCH v4 06/20] riscv: add ISA extension parsing for vector crypto Clément Léger
2023-11-14 14:12 ` [PATCH v4 07/20] riscv: hwprobe: export vector crypto ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 08/20] dt-bindings: riscv: add vector crypto ISA extensions description Clément Léger
2023-11-14 14:12 ` [PATCH v4 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] Clément Léger
2023-11-14 14:12 ` Clément Léger [this message]
2023-11-14 14:12 ` [PATCH v4 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description Clément Léger
2023-11-14 14:12 ` [PATCH v4 12/20] riscv: add ISA extension parsing for Zihintntl Clément Léger
2023-11-14 14:12 ` [PATCH v4 13/20] riscv: hwprobe: export Zhintntl ISA extension Clément Léger
2023-11-14 14:12 ` [PATCH v4 14/20] dt-bindings: riscv: add Zihintntl ISA extension description Clément Léger
2023-11-14 14:12 ` [PATCH v4 15/20] riscv: add ISA extension parsing for Zvfh[min] Clément Léger
2023-11-14 14:12 ` [PATCH v4 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description Clément Léger
2023-11-14 14:12 ` [PATCH v4 18/20] riscv: add ISA extension parsing for Zfa Clément Léger
2023-11-14 14:12 ` [PATCH v4 19/20] riscv: hwprobe: export Zfa ISA extension Clément Léger
2023-11-14 14:12 ` [PATCH v4 20/20] dt-bindings: riscv: add Zfa ISA extension description Clément Léger
2023-11-22 16:16 ` [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Conor Dooley
2023-12-12 22:20 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231114141256.126749-11-cleger@rivosinc.com \
--to=cleger@rivosinc.com \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=evan@rivosinc.com \
--cc=jerry.shih@sifive.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=sameo@rivosinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®