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From: "William A. Kennington III" <william@wkennington.com>
To: tmaimon77@gmail.com, tali.perry1@gmail.com,
	avifishman70@gmail.com, linus.walleij@linaro.org, joel@jms.id.au
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
	"William A . Kennington III" <william@wkennington.com>
Subject: [PATCH] pinctrl: npcm7xx: prevent glitch when setting the GPIO to output high
Date: Wed, 15 Nov 2023 13:12:09 -0800	[thread overview]
Message-ID: <20231115211209.1683449-1-william@wkennington.com> (raw)

From: Tomer Maimon <tmaimon77@gmail.com>

Enable GPIO output after setting the output value to prevent a glitch
when pinctrl driver sets gpio pin to output high and the pin is in
the default state (high->low->high).

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: William A. Kennington III <william@wkennington.com>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 1e658721aaba..62a46d824b46 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1790,8 +1790,8 @@ static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
 		bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
 		break;
 	case PIN_CONFIG_OUTPUT:
-		iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
 		bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
+		iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
 		break;
 	case PIN_CONFIG_DRIVE_PUSH_PULL:
 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
-- 
2.43.0.rc0.421.g78406f8d94-goog


             reply	other threads:[~2023-11-15 21:12 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-15 21:12 William A. Kennington III [this message]
2023-11-24  9:42 ` Linus Walleij

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