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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4B.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Wed, 22 Nov 2023 05:31:01 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 21 Nov 2023 23:31:00 -0600 From: Nava kishore Manne To: , , , , , , , , , , Subject: [RFC 0/2]fpga: Add fpga configuration support from a pre-allocated dma-able buffer Date: Wed, 22 Nov 2023 11:00:33 +0530 Message-ID: <20231122053035.3758124-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|CY8PR12MB8068:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d9a0210-bada-4d6c-d55d-08dbeb1c36f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2023 05:31:01.6215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d9a0210-bada-4d6c-d55d-08dbeb1c36f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8068 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Lots of embedded systems have memory constraints but they need to load very large configuration files.The FPGA subsystem allows drivers to request this configuration image be loaded from the filesystem,but this requires that the entire configuration data be loaded into kernel memory first before it's provided to the driver.This can lead to a situation where we map the configuration data twice, once to load the configuration data into kernel memory and once to copy the configuration data into the final resting place which is nothing but a dma-able continuous buffer. This creates needless memory pressure and delays due to multiple copies. Let's add a dmabuf handling support to the fpga manager framework that allows drivers to load the Configuration data directly from a pre-allocated buffer. This skips the intermediate step of allocating a buffer in kernel memory to hold the Configuration data. This implementation allows the lower-level drivers to request the FPGA Configuration image be loaded from pre-allocated dma-able continuous buffer and also it avoid needless memory pressure and delays due to multiple copies. Please take a look at the changes and let us know if any improvements are required. Nava kishore Manne (2): fpga: support loading from a pre-allocated buffer fpga: versal: Use the scatterlist interface drivers/fpga/fpga-mgr.c | 113 ++++++++++++++++++++++++++++++++++ drivers/fpga/versal-fpga.c | 13 ++++ include/linux/fpga/fpga-mgr.h | 10 +++ 3 files changed, 136 insertions(+) -- 2.25.1