From: Raag Jadav <raag.jadav@intel.com>
To: mika.westerberg@linux.intel.com,
andriy.shevchenko@linux.intel.com, linus.walleij@linaro.org
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
Raag Jadav <raag.jadav@intel.com>
Subject: [PATCH v1] pinctrl: tangier: simplify locking using cleanup helpers
Date: Thu, 23 Nov 2023 19:32:12 +0530 [thread overview]
Message-ID: <20231123140212.12135-1-raag.jadav@intel.com> (raw)
Use lock guards from cleanup.h to simplify locking.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/pinctrl/intel/pinctrl-tangier.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-tangier.c b/drivers/pinctrl/intel/pinctrl-tangier.c
index 26e34ec0a972..2cb0b4758269 100644
--- a/drivers/pinctrl/intel/pinctrl-tangier.c
+++ b/drivers/pinctrl/intel/pinctrl-tangier.c
@@ -9,6 +9,7 @@
*/
#include <linux/bits.h>
+#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
@@ -220,7 +221,6 @@ static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev,
const struct intel_pingroup *grp = &tp->groups[group];
u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
u32 mask = BUFCFG_PINMODE_MASK;
- unsigned long flags;
unsigned int i;
/*
@@ -232,11 +232,11 @@ static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev,
return -EBUSY;
}
+ guard(raw_spinlock_irqsave)(&tp->lock);
+
/* Now enable the mux setting for each pin in the group */
- raw_spin_lock_irqsave(&tp->lock, flags);
for (i = 0; i < grp->grp.npins; i++)
tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask);
- raw_spin_unlock_irqrestore(&tp->lock, flags);
return 0;
}
@@ -248,14 +248,13 @@ static int tng_gpio_request_enable(struct pinctrl_dev *pctldev,
struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
u32 mask = BUFCFG_PINMODE_MASK;
- unsigned long flags;
if (!tng_buf_available(tp, pin))
return -EBUSY;
- raw_spin_lock_irqsave(&tp->lock, flags);
+ guard(raw_spinlock_irqsave)(&tp->lock);
+
tng_update_bufcfg(tp, pin, bits, mask);
- raw_spin_unlock_irqrestore(&tp->lock, flags);
return 0;
}
@@ -360,7 +359,6 @@ static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
unsigned int param = pinconf_to_config_param(config);
unsigned int arg = pinconf_to_config_argument(config);
u32 mask, term, value = 0;
- unsigned long flags;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
@@ -432,9 +430,9 @@ static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
return -EINVAL;
}
- raw_spin_lock_irqsave(&tp->lock, flags);
+ guard(raw_spinlock_irqsave)(&tp->lock);
+
tng_update_bufcfg(tp, pin, value, mask);
- raw_spin_unlock_irqrestore(&tp->lock, flags);
return 0;
}
base-commit: e58e519b80ba79cd73abb1d631d429b7322ac9cb
--
2.17.1
next reply other threads:[~2023-11-23 14:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-23 14:02 Raag Jadav [this message]
2023-11-23 14:28 ` Mika Westerberg
2023-11-24 11:09 ` Andy Shevchenko
2023-11-24 12:08 ` Raag Jadav
2023-11-24 12:32 ` Andy Shevchenko
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