From: Dario Binacchi <dario.binacchi@amarulasolutions.com>
To: linux-kernel@vger.kernel.org
Cc: "Dario Binacchi" <dario.binacchi@amarulasolutions.com>,
"Christophe Leroy" <christophe.leroy@csgroup.eu>,
"Kumar Gala" <galak@kernel.crashing.org>,
"Michael Ellerman" <mpe@ellerman.id.au>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Pali Rohár" <pali@kernel.org>, "Rob Herring" <robh@kernel.org>,
"Scott Wood" <oss@buserror.net>,
"Timur Tabi" <timur@freescale.com>,
"Zhicheng Fan" <b32736@freescale.com>,
linuxppc-dev@lists.ozlabs.org
Subject: [PATCH] powerpc/85xx: Fix typo in code comment
Date: Fri, 24 Nov 2023 11:02:37 +0100 [thread overview]
Message-ID: <20231124100241.660374-1-dario.binacchi@amarulasolutions.com> (raw)
s/singals/signals/
Fixes: 04e358d896a7 ("powerpc/85xx: Add Quicc Engine support for p1025rdb")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ec9f60fbebc7..e0cec670d8db 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -76,7 +76,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
/* P1025 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
- * and QE12 for QE MII management singals in PMUXCR
+ * and QE12 for QE MII management signals in PMUXCR
* register.
*/
setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
--
2.42.0
next reply other threads:[~2023-11-24 10:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-24 10:02 Dario Binacchi [this message]
2023-11-24 13:08 ` Christophe Leroy
2023-11-24 13:14 ` Dario Binacchi
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