From: Jerry Shih <jerry.shih@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, herbert@gondor.apana.org.au,
davem@davemloft.net, conor.dooley@microchip.com,
ebiggers@kernel.org, ardb@kernel.org, conor@kernel.org
Cc: heiko@sntech.de, phoebe.chen@sifive.com, hongrong.hsu@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-crypto@vger.kernel.org
Subject: [PATCH v3 01/12] RISC-V: add helper function to read the vector VLEN
Date: Tue, 5 Dec 2023 17:27:50 +0800 [thread overview]
Message-ID: <20231205092801.1335-2-jerry.shih@sifive.com> (raw)
In-Reply-To: <20231205092801.1335-1-jerry.shih@sifive.com>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.
The vector code already includes a variable riscv_v_vsize that contains
the value of "32 vector registers with vlenb length" that gets filled
during boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".
So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
---
arch/riscv/include/asm/vector.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 9fb2dea66abd..1fd3e5510b64 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -244,4 +244,15 @@ void kernel_vector_allow_preemption(void);
#define kernel_vector_allow_preemption() do {} while (0)
#endif
+/*
+ * Return the implementation's vlen value.
+ *
+ * riscv_v_vsize contains the value of "32 vector registers with vlenb length"
+ * so rebuild the vlen value in bits from it.
+ */
+static inline int riscv_vector_vlen(void)
+{
+ return riscv_v_vsize / 32 * 8;
+}
+
#endif /* ! __ASM_RISCV_VECTOR_H */
--
2.28.0
next prev parent reply other threads:[~2023-12-05 9:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 9:27 [PATCH v3 00/12] RISC-V: provide some accelerated cryptography implementations using vector extensions Jerry Shih
2023-12-05 9:27 ` Jerry Shih [this message]
2023-12-05 9:27 ` [PATCH v3 02/12] RISC-V: hook new crypto subdir into build-system Jerry Shih
2023-12-05 9:27 ` [PATCH v3 03/12] RISC-V: crypto: add OpenSSL perl module for vector instructions Jerry Shih
2023-12-05 9:27 ` [PATCH v3 04/12] RISC-V: crypto: add Zvkned accelerated AES implementation Jerry Shih
2023-12-05 9:27 ` [PATCH v3 05/12] crypto: simd - Update `walksize` in simd skcipher Jerry Shih
2023-12-05 9:27 ` [PATCH v3 06/12] RISC-V: crypto: add accelerated AES-CBC/CTR/ECB/XTS implementations Jerry Shih
2023-12-05 9:27 ` [PATCH v3 07/12] RISC-V: crypto: add Zvkg accelerated GCM GHASH implementation Jerry Shih
2023-12-05 9:27 ` [PATCH v3 08/12] RISC-V: crypto: add Zvknha/b accelerated SHA224/256 implementations Jerry Shih
2023-12-05 9:27 ` [PATCH v3 09/12] RISC-V: crypto: add Zvknhb accelerated SHA384/512 implementations Jerry Shih
2023-12-05 9:27 ` [PATCH v3 10/12] RISC-V: crypto: add Zvksed accelerated SM4 implementation Jerry Shih
2023-12-05 9:28 ` [PATCH v3 11/12] RISC-V: crypto: add Zvksh accelerated SM3 implementation Jerry Shih
2023-12-05 9:28 ` [PATCH v3 12/12] RISC-V: crypto: add Zvkb accelerated ChaCha20 implementation Jerry Shih
2023-12-06 0:46 ` [PATCH v3 00/12] RISC-V: provide some accelerated cryptography implementations using vector extensions Eric Biggers
2023-12-06 7:02 ` Jerry Shih
2023-12-06 7:41 ` Eric Biggers
2023-12-06 17:07 ` Palmer Dabbelt
2023-12-07 15:31 ` Andy Chiu
2023-12-22 5:48 ` Eric Biggers
2023-12-30 3:51 ` Eric Biggers
2024-01-02 5:16 ` Jerry Shih
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