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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id k14-20020a5d524e000000b00333479734a7sm13480574wrc.99.2023.12.13.06.53.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:53:35 -0800 (PST) Date: Wed, 13 Dec 2023 15:53:34 +0100 From: Andrew Jones To: Yong-Xuan Wang Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, greentime.hu@sifive.com, vincent.chen@sifive.com, tjytimi@163.com, alex@ghiti.fr, conor.dooley@microchip.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Guo Ren , Daniel Henrique Barboza , Heiko Stuebner , Jisheng Zhang , Andrew Morton , Alexandre Ghiti , Kemeng Shi , David Hildenbrand , Charlie Jenkins , Sergey Matyukevich , "Matthew Wilcox (Oracle)" , Qinglin Pan , Rick Edgecombe , Evan Green , Sunil V L , linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/4] RISC-V: Detect and Enable Svadu Extension Support Message-ID: <20231213-0160e1e392ad2172c27807c2@orel> References: <20231102120129.11261-1-yongxuan.wang@sifive.com> <20231102120129.11261-2-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231102120129.11261-2-yongxuan.wang@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 02, 2023 at 12:01:22PM +0000, Yong-Xuan Wang wrote: > Svadu is a RISC-V extension for hardware updating of PTE A/D bits. > > In this patch we detect Svadu extension support from DTB and > add arch_has_hw_pte_young() to enable optimization in MGLRU and > __wp_page_copy_user() if Svadu extension is available. > > Co-developed-by: Jinyu Tang > Signed-off-by: Jinyu Tang > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Conor Dooley > --- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/pgtable.h | 6 ++++++ > arch/riscv/kernel/cpufeature.c | 1 + > 4 files changed, 9 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 777cb8299551..e6935fd48c0c 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -194,6 +194,7 @@ > /* xENVCFG flags */ > #define ENVCFG_STCE (_AC(1, ULL) << 63) > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) > +#define ENVCFG_ADUE (_AC(1, ULL) << 61) > #define ENVCFG_CBZE (_AC(1, UL) << 7) > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > #define ENVCFG_CBIE_SHIFT 4 > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index b7b58258f6c7..1013661d6516 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -58,6 +58,7 @@ > #define RISCV_ISA_EXT_ZICSR 40 > #define RISCV_ISA_EXT_ZIFENCEI 41 > #define RISCV_ISA_EXT_ZIHPM 42 > +#define RISCV_ISA_EXT_SVADU 43 > > #define RISCV_ISA_EXT_MAX 64 > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index b2ba3f79cfe9..028b700cd27b 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) > return __pgprot(prot); > } > > +#define arch_has_hw_pte_young arch_has_hw_pte_young > +static inline bool arch_has_hw_pte_young(void) > +{ > + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); > +} > + > /* > * THP functions > */ > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1cfbba65d11a..ead378c04991 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > -- > 2.17.1 > Reviewed-by: Andrew Jones