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From:   Conor Dooley <conor@kernel.org>
To:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
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        Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc:     conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
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        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
        Geert Uytterhoeven <geert@linux-m68k.org>
Subject: Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
Date:   Wed, 13 Dec 2023 15:42:44 +0000
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From: Conor Dooley <conor.dooley@microchip.com>

On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> Now that the driver for the SiFive cache controller supports manual
> flushing as non-standard cache operations[1] we can add an errata option
> for the StarFive JH7100 SoC and update the device tree with the cache
> controller, dedicated DMA pool and add MMC nodes for the SD-card and
> wifi.
> 
> This series needs the following commit in [1] to work properly:
> 
> [...]

Applied to riscv-cache-for-next, thanks!

[1/8] riscv: errata: Add StarFive JH7100 errata
      https://git.kernel.org/conor/c/64fc984a8a54

Thanks,
Conor.