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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id h15-20020a1709060f4f00b00a26e1122762sm8754870ejj.192.2024.01.02.03.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 03:18:54 -0800 (PST) Date: Tue, 2 Jan 2024 12:18:53 +0100 From: Andrew Jones To: guoren@kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, panqinglin2020@iscas.ac.cn, bjorn@rivosinc.com, conor.dooley@microchip.com, leobras@redhat.com, peterz@infradead.org, keescook@chromium.org, wuwei2016@iscas.ac.cn, xiaoguang.xing@sophgo.com, chao.wei@sophgo.com, unicorn_wang@outlook.com, uwu@icenowy.me, jszhang@kernel.org, wefu@redhat.com, atishp@atishpatra.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guo Ren Subject: Re: [PATCH V2 3/3] riscv: xchg: Prefetch the destination word for sc.w Message-ID: <20240102-81391283df04c430d76c0eb0@orel> References: <20231231082955.16516-1-guoren@kernel.org> <20231231082955.16516-4-guoren@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231231082955.16516-4-guoren@kernel.org> On Sun, Dec 31, 2023 at 03:29:53AM -0500, guoren@kernel.org wrote: > From: Guo Ren > > The cost of changing a cacheline from shared to exclusive state can be > significant, especially when this is triggered by an exclusive store, > since it may result in having to retry the transaction. > > This patch makes use of prefetch.w to prefetch cachelines for write > prior to lr/sc loops when using the xchg_small atomic routine. > > This patch is inspired by commit: 0ea366f5e1b6 ("arm64: atomics: > prefetch the destination word for write prior to stxr"). > > Signed-off-by: Guo Ren > Signed-off-by: Guo Ren > --- > arch/riscv/include/asm/cmpxchg.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index 26cea2395aae..d7b9d7951f08 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -10,6 +10,7 @@ > > #include > #include > +#include > > #define __arch_xchg_masked(prepend, append, r, p, n) \ Are you sure this is based on v6.7-rc7? Because I don't see this macro. > ({ \ > @@ -23,6 +24,7 @@ > \ > __asm__ __volatile__ ( \ > prepend \ > + PREFETCHW_ASM(%5) \ > "0: lr.w %0, %2\n" \ > " and %1, %0, %z4\n" \ > " or %1, %1, %z3\n" \ > @@ -30,7 +32,7 @@ > " bnez %1, 0b\n" \ > append \ > : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \ > - : "rJ" (__newx), "rJ" (~__mask) \ > + : "rJ" (__newx), "rJ" (~__mask), "rJ" (__ptr32b) \ I'm pretty sure we don't want to allow the J constraint for __ptr32b. > : "memory"); \ > \ > r = (__typeof__(*(p)))((__retx & __mask) >> __s); \ > -- > 2.40.1 > Thanks, drew