From: Conor Dooley <conor@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: Re: [v2 03/10] drivers/perf: riscv: Read upper bits of a firmware counter
Date: Tue, 9 Jan 2024 18:24:20 +0000 [thread overview]
Message-ID: <20240109-saddlebag-daylight-306f7eab1c1f@spud> (raw)
In-Reply-To: <20231229214950.4061381-4-atishp@rivosinc.com>
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On Fri, Dec 29, 2023 at 01:49:43PM -0800, Atish Patra wrote:
> SBI v2.0 introduced a explicit function to read the upper 32 bits
> for any firmwar counter width that is longer than 32bits.
> This is only applicable for RV32 where firmware counter can be
> 64 bit.
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> drivers/perf/riscv_pmu_sbi.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 16acd4dcdb96..646604f8c0a5 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -35,6 +35,8 @@
> PMU_FORMAT_ATTR(event, "config:0-47");
> PMU_FORMAT_ATTR(firmware, "config:63");
>
> +static bool sbi_v2_available;
> +
> static struct attribute *riscv_arch_formats_attr[] = {
> &format_attr_event.attr,
> &format_attr_firmware.attr,
> @@ -488,16 +490,23 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event)
> struct hw_perf_event *hwc = &event->hw;
> int idx = hwc->idx;
> struct sbiret ret;
> - union sbi_pmu_ctr_info info;
> u64 val = 0;
> + union sbi_pmu_ctr_info info = pmu_ctr_list[idx];
>
> if (pmu_sbi_is_fw_event(event)) {
> ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
> hwc->idx, 0, 0, 0, 0, 0);
> - if (!ret.error)
> - val = ret.value;
> + if (ret.error)
> + return val;
A nit perhaps, but can you just make this return 0 please? I think it
makes the code more obvious in its intent.
Otherwise I think you've satisfied the issues that I had with the
previous iteration:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> +
> + val = ret.value;
> + if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) {
> + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI,
> + hwc->idx, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + val |= ((u64)ret.value << 32);
> + }
> } else {
> - info = pmu_ctr_list[idx];
> val = riscv_pmu_ctr_read_csr(info.csr);
> if (IS_ENABLED(CONFIG_32BIT))
> val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val;
> @@ -1108,6 +1117,9 @@ static int __init pmu_sbi_devinit(void)
> return 0;
> }
>
> + if (sbi_spec_version >= sbi_mk_version(2, 0))
> + sbi_v2_available = true;
> +
> ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
> "perf/riscv/pmu:starting",
> pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
> --
> 2.34.1
>
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next prev parent reply other threads:[~2024-01-09 18:24 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-29 21:49 [v2 00/10] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra
2023-12-29 21:49 ` [v2 01/10] RISC-V: Fix the typo in Scountovf CSR name Atish Patra
2023-12-29 21:49 ` [v2 02/10] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra
2023-12-29 21:49 ` [v2 03/10] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra
2023-12-30 7:55 ` Anup Patel
2024-01-09 18:24 ` Conor Dooley [this message]
2023-12-29 21:49 ` [v2 04/10] RISC-V: Add SBI PMU snapshot definitions Atish Patra
2023-12-29 21:49 ` [v2 05/10] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra
2023-12-30 7:58 ` Anup Patel
2024-01-09 18:30 ` Conor Dooley
2023-12-29 21:49 ` [v2 06/10] RISC-V: KVM: No need to update the counter value during reset Atish Patra
2023-12-30 8:00 ` Anup Patel
2023-12-29 21:49 ` [v2 07/10] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra
2023-12-30 8:01 ` Anup Patel
2023-12-29 21:49 ` [v2 08/10] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra
2023-12-30 8:05 ` Anup Patel
2023-12-29 21:49 ` [v2 09/10] RISC-V: KVM: Add perf sampling support for guests Atish Patra
2023-12-30 8:09 ` Anup Patel
2024-01-10 12:38 ` Vladimir Isaev
2024-01-10 15:23 ` Atish Kumar Patra
2023-12-29 21:49 ` [v2 10/10] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra
2023-12-30 8:10 ` Anup Patel
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