From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
<joro@8bytes.org>, <jgg@nvidia.com>
Cc: <yi.l.liu@intel.com>, <kevin.tian@intel.com>,
<nicolinc@nvidia.com>, <eric.auger@redhat.com>,
<vasant.hegde@amd.com>, <jon.grimm@amd.com>,
<santosh.shukla@amd.com>, <Dhaval.Giani@amd.com>,
<pandoh@google.com>, <loganodell@google.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [RFCv2 PATCH 1/7] iommu/amd: Introduce struct gcr3_tbl_info.giov
Date: Thu, 11 Jan 2024 18:06:40 -0600 [thread overview]
Message-ID: <20240112000646.98001-2-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20240112000646.98001-1-suravee.suthikulpanit@amd.com>
To track DTE[GIOV] programming during IOMMU domain attach, also add logic
to determine if the GIOV is required, and set the variable accordinglly.
This is also a preparation for adding nested domain support, where the GIOV
setting is determined by the child domain.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/amd_iommu_types.h | 1 +
drivers/iommu/amd/iommu.c | 11 +++++++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 3dc39bbc05fc..ff56c857f6ad 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -536,6 +536,7 @@ struct gcr3_tbl_info {
u64 *gcr3_tbl; /* Guest CR3 table */
int glx; /* Number of levels for GCR3 table */
u32 pasid_cnt; /* Track attached PASIDs */
+ bool giov; /* Track DTE[GIOV] */
};
struct amd_io_pgtable {
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 4e4ff1550cf3..b9759f6d8be2 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1990,8 +1990,7 @@ static void set_dte_entry(struct amd_iommu *iommu,
((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT);
}
- /* GIOV is supported with V2 page table mode only */
- if (pdom_is_v2_pgtbl_mode(domain))
+ if (gcr3_info->giov)
pte_root |= DTE_FLAG_GIOV;
}
@@ -2067,6 +2066,14 @@ static int do_attach(struct iommu_dev_data *dev_data,
free_gcr3_table(dev_data);
return ret;
}
+
+ /*
+ * GIOV is required for PD_MODE_V2 because we need
+ * to support the case where the end-point device
+ * does not have PASID in the TLP prefix when setting
+ * up to use the v2 table.
+ */
+ dev_data->gcr3_info.giov = true;
}
/* Update device table */
--
2.34.1
next prev parent reply other threads:[~2024-01-12 0:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-12 0:06 [RFCv2 PATCH 0/7] iommu/amd: Introduce hardware info reporting and nested translation support Suravee Suthikulpanit
2024-01-12 0:06 ` Suravee Suthikulpanit [this message]
2024-03-08 13:48 ` [RFCv2 PATCH 1/7] iommu/amd: Introduce struct gcr3_tbl_info.giov Jason Gunthorpe
2024-01-12 0:06 ` [RFCv2 PATCH 2/7] iommu/amd: Refactor set_dte_entry Suravee Suthikulpanit
2024-01-22 8:39 ` Tian, Kevin
2024-03-08 13:51 ` Jason Gunthorpe
2024-01-12 0:06 ` [RFCv2 PATCH 3/7] iommu/amd: Update PASID, GATS, and GLX feature related macros Suravee Suthikulpanit
2024-03-08 13:55 ` Jason Gunthorpe
2024-01-12 0:06 ` [RFCv2 PATCH 4/7] iommu/amd: Add support for hw_info for iommu capability query Suravee Suthikulpanit
2024-03-08 13:57 ` Jason Gunthorpe
2024-01-12 0:06 ` [RFCv2 PATCH 5/7] iommufd: Introduce data struct for AMD nested domain allocation Suravee Suthikulpanit
2024-01-22 8:46 ` Tian, Kevin
2024-03-08 13:58 ` Jason Gunthorpe
2024-01-12 0:06 ` [RFCv2 PATCH 6/7] iommu/amd: Add nested domain allocation support Suravee Suthikulpanit
2024-01-22 8:52 ` Tian, Kevin
2024-03-08 14:04 ` Jason Gunthorpe
2024-01-12 0:06 ` [RFCv2 PATCH 7/7] iommu/amd: Add nested domain attach/detach support Suravee Suthikulpanit
2024-01-22 8:56 ` Tian, Kevin
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