drivers/gpu/drm/xe/xe_gt_pagefault.c:340:17: warning: writing 16 bytes into a region of size 0

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   052d534373b7ed33712a63d5e17b2b6cdbce84fd
commit: 5c0553cdc811bb6af4f1bfef178bd07fc16a797e drm/xe: Replace XE_WARN_ON with drm_warn when just printing a string
date:   4 weeks ago
config: s390-randconfig-r071-20240116 (https://download.01.org/0day-ci/archive/20240116/202401161031.hjGJHMiJ-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240116/202401161031.hjGJHMiJ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202401161031.hjGJHMiJ-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/xe/xe_gt_pagefault.c: In function 'xe_guc_pagefault_handler':
>> drivers/gpu/drm/xe/xe_gt_pagefault.c:340:17: warning: writing 16 bytes into a region of size 0 [-Wstringop-overflow=]
     340 |                 memcpy(pf_queue->data + pf_queue->tail, msg, len * sizeof(u32));
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   In file included from drivers/gpu/drm/xe/xe_device_types.h:16,
                    from drivers/gpu/drm/xe/xe_vm_types.h:16,
                    from drivers/gpu/drm/xe/xe_bo.h:11,
                    from drivers/gpu/drm/xe/xe_gt_pagefault.c:15:
   drivers/gpu/drm/xe/xe_gt_types.h:102:25: note: at offset [1216, 265396] into destination object 'tile' of size 8
     102 |         struct xe_tile *tile;
         |                         ^~~~


vim +340 drivers/gpu/drm/xe/xe_gt_pagefault.c

dd08ebf6c3525a Matthew Brost   2023-03-30  321  
dd08ebf6c3525a Matthew Brost   2023-03-30  322  int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len)
dd08ebf6c3525a Matthew Brost   2023-03-30  323  {
dd08ebf6c3525a Matthew Brost   2023-03-30  324  	struct xe_gt *gt = guc_to_gt(guc);
5c0553cdc811bb Francois Dugast 2023-09-12  325  	struct xe_device *xe = gt_to_xe(gt);
dd08ebf6c3525a Matthew Brost   2023-03-30  326  	struct pf_queue *pf_queue;
dd08ebf6c3525a Matthew Brost   2023-03-30  327  	unsigned long flags;
dd08ebf6c3525a Matthew Brost   2023-03-30  328  	u32 asid;
dd08ebf6c3525a Matthew Brost   2023-03-30  329  	bool full;
dd08ebf6c3525a Matthew Brost   2023-03-30  330  
dd08ebf6c3525a Matthew Brost   2023-03-30  331  	if (unlikely(len != PF_MSG_LEN_DW))
dd08ebf6c3525a Matthew Brost   2023-03-30  332  		return -EPROTO;
dd08ebf6c3525a Matthew Brost   2023-03-30  333  
dd08ebf6c3525a Matthew Brost   2023-03-30  334  	asid = FIELD_GET(PFD_ASID, msg[1]);
dd08ebf6c3525a Matthew Brost   2023-03-30  335  	pf_queue = &gt->usm.pf_queue[asid % NUM_PF_QUEUE];
dd08ebf6c3525a Matthew Brost   2023-03-30  336  
dd08ebf6c3525a Matthew Brost   2023-03-30  337  	spin_lock_irqsave(&pf_queue->lock, flags);
dd08ebf6c3525a Matthew Brost   2023-03-30  338  	full = pf_queue_full(pf_queue);
dd08ebf6c3525a Matthew Brost   2023-03-30  339  	if (!full) {
dd08ebf6c3525a Matthew Brost   2023-03-30 @340  		memcpy(pf_queue->data + pf_queue->tail, msg, len * sizeof(u32));
dd08ebf6c3525a Matthew Brost   2023-03-30  341  		pf_queue->tail = (pf_queue->tail + len) % PF_QUEUE_NUM_DW;
dd08ebf6c3525a Matthew Brost   2023-03-30  342  		queue_work(gt->usm.pf_wq, &pf_queue->worker);
dd08ebf6c3525a Matthew Brost   2023-03-30  343  	} else {
5c0553cdc811bb Francois Dugast 2023-09-12  344  		drm_warn(&xe->drm, "PF Queue full, shouldn't be possible");
dd08ebf6c3525a Matthew Brost   2023-03-30  345  	}
dd08ebf6c3525a Matthew Brost   2023-03-30  346  	spin_unlock_irqrestore(&pf_queue->lock, flags);
dd08ebf6c3525a Matthew Brost   2023-03-30  347  
dd08ebf6c3525a Matthew Brost   2023-03-30  348  	return full ? -ENOSPC : 0;
dd08ebf6c3525a Matthew Brost   2023-03-30  349  }
dd08ebf6c3525a Matthew Brost   2023-03-30  350  

:::::: The code at line 340 was first introduced by commit
:::::: dd08ebf6c3525a7ea2186e636df064ea47281987 drm/xe: Introduce a new DRM driver for Intel GPUs

:::::: TO: Matthew Brost <matthew.brost@intel.com>
:::::: CC: Rodrigo Vivi <rodrigo.vivi@intel.com>

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